SX User’s Manual Rev. 3.1 38 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 2 Architecture PSA Bit: Prescaler Assignment Clear the PSA bit to 0 to have the internal prescaler operate with the Real-Time Clock/Counter. In that
case, the RTCC counter is incremented once every n instruction cycles, with the number n determined
by the PS2:PS0 bits; and the Watchdog timer operates at the default rate. Set the PSA bit to 1 to have the internal prescaler operate with the Watchdog timer. In that case, a
Watchdog  reset  is  generated  after  n  timeouts  of  the  Watchdog  timer  register,  with  the  number  n
determined by the PS2:PS0 bits; and the RTCC register is incremented once per instruction cycle or
external event. PS2:PS0 Field: Prescaler Divide-By Factor Use this bit field in conjunction with the PSA bit to specify an operating rate for the RTCC timer or
Watchdog  timer  that  is  lower  than  the  default  rate.  Table 2-6  shows  the  clock  divide-by  factors
determined by these bits. Note that for a given setting, the divide-by factor depends on whether you
use the prescaler register with the RTCC timer (PSA=0) or with the Watchdog timer (PSA=1). For the
RTCC timer, the timer is incremented once every 2, 4, 8, ... or 256 instruction cycles or external events.
For  the  Watchdog  timer,  a  Watchdog  reset  is  triggered  after  1,  2,  4,  ...  or  128  overflows  of  the
Watchdog timer register. For detailed information on the Real-Time Clock/Counter and Watchdog timer, see Chapter 6. Table 2-6  Prescaler Divide-By Factors PS2:PS0       RTCC Timer Input
Divide-By Factor (PSA=0)  Watchdog Timer Output
Divide-By Factor (PSA=1) 000 2 1 (timeout = 0.016 sec) 001 4 2 (timeout = 0.032 sec) 010 8 4 (timeout = 0.064 sec) 011 16 8 (timeout = 0.128 sec) 100 32 16 (timeout = 0.256 sec) 101 64 32 (timeout = 0.5 sec) 110 128 64 (timeout = 1.0 sec) 111 256 128 (timeout = 2.0 sec)