© 2000 Scenix Semiconductor, Inc. All rights reserved.
39
SX User’s Manual Rev. 3.1
www.scenix.com
Chapter 2 Architecture
2.5
Instruction Execution Pipeline
The CPU executes in program in a 4-stage pipeline consisting of the following stages:
•
Fetch the instruction from program memory.
•
Decode the instruction opcode.
•
Execute the operation.
•
Write the result to destination register.
Each execution stage requires one instruction cycle. Although it takes four cycles to complete the
execution of each instruction, an overall throughput of one instruction per clock cycle is achieved by
overlapping successive operations in the pipeline. For example, Table 2-7 shows the sequence of
operations carried out as the CPU executes the first six instructions of a program.
As long as the normal flow of the program is not interrupted, the device performs four pipeline
operations in parallel, thus achieving an overall throughput of one instruction per clock cycle, or 50
MIPS with a 50 MHz clock in the “turbo” clocking mode.
2.5.1
Clocking Modes
The SX device can be configured to operate in either the “turbo” or “compatible” mode. In the “turbo”
mode, instructions are executed at the rate of one per clock cycle, and one clock cycle is the same as
one instruction cycle. In the “compatible” mode (SX18/20/28AC and SX18/20/28AC75 devices only),
instructions are executed at the rate of one per four clock cycles, and four device clock cycles are
required for each instruction cycle. For more information on these clocking modes, see Section 4.2.1.
Table 2-7 Pipeline Execution Sequence
Program
Instruction
Clock
Cycle 1
Clock
Cycle 2
Clock
Cycle 3
Clock
Cycle 4
Clock
Cycle 5
Clock
Cycle 6
etc.
1st instruction
Fetch
Decode
Execute
Write
2nd instruction
Fetch
Decode
Execute
Write
3rd instruction
Fetch
Decode
Execute
Write
4th instruction
Fetch
Decode
Execute
...
5th instruction
Fetch
Decode
...
6th instruction
Fetch
...
