SX User’s Manual Rev. 3.1 22 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 2 Architecture The SX device uses a modified Harvard architecture, in which the program and data are stored in
separate  memory  spaces.  The  advantage  of  this  architecture  is  that  instruction  fetches  and  data
transfers  can  be  overlapped  with  a  multi-stage  pipeline,  which  means  the  next  instruction  can  be
fetched from program memory while the current instruction is being executed uses data from the data
memory. This  device  has  a  “modified” Harvard  architecture  because  instructions  are available  for
transferring data from the program memory to the data memory. 2.2 Program Memory The program memory holds the application program for the device. It is an electrically erasable, flash-
programmed memory containing 2,048 words for the SX18/20/28AC and SX18/20/28AC75 devices
or 4,096 words for the SX48/52BD, with 12 bits per word. Each memory location holds a single 12-
bit instruction opcode or 12 bits of fixed data that can be accessed by the program. The memory can
be programmed and reprogrammed through the device oscillator pins, even with the device installed
in the target system. The program memory is addressed by the program counter, a register of 11 bits for the SX18/20/28AC
and SX18/20/28AC75 or 12 bits for the SX48/52BD. Operation of the program counter is described in
detail in Section 2.6. 2.3 Data Memory The data memory is a RAM-based register set consisting of general-purpose registers and dedicated-
purpose registers. The number of registers depends on the SX device type. The SX18/20/28AC and
SX18/20/28AC75 devices have 136 general-purpose registers and eight dedicated-purpose registers.
The SX48/52BD has 262 general-purpose registers and ten dedicated-purpose registers. All of these
registers are eight bits wide. The registers are organized into banks, allowing the SX instructions to
address the registers using just five bits of the 12-bit instruction opcode. Because the registers are organized into banks or “files,” these memory-mapped registers are called
“file registers.” In the descriptions of the SX instructions in Chapter 3, the abbreviation “fr” represents
a 5-bit register selection value encoded into the instruction opcode. 2.3.1 Banks The SX device can be programmed to use any one of the data memory banks at any given time. The
high-order bits in the File Select Register (FSR) specify the current bank number. To change from one
bank to another, the program can either write an eight-bit value to the FSR register or use the “bank”
instruction.  The  “bank”  instruction  writes  the  three  high-order  bits  in  the  FSR  register  without
affecting the other bits in the register.