© 2000 Scenix Semiconductor, Inc. All rights reserved. 155 SX User’s Manual Rev. 3.1 www.scenix.com Chapter 6 Timers and Interrupts register.  Table 6-1  lists  the  PS2:PS0  settings  and  the  corresponding  divide-by  factors  and  typical
timeout periods. 6.3.2 Watchdog Operation in the Power Down Mode The Watchdog timer can operate even during the power down mode. This feature causes an automatic
wakeup from the power down mode after the Watchdog timeout period has elapsed. The Watchdog
circuit can continue to operate in power down mode because it is driven by its own on-chip oscillator. If you do not need to use the Watchdog timer, you can disable it by clearing the WDTE bit in the FUSE
word register. Doing so reduces power consumption in the power down mode because the Watchdog
oscillator and counter no longer operate. 6.4     Interrupts An interrupt is a condition that causes a CPU to stop its normal program execution and perform a
separate “service” routine that handles the cause of the interrupt condition. An interrupt can occur at
any point in the program and is typically triggered by an event that can happen at any time. An interrupt causes the CPU to save the program context (program counter, W, STATUS, and FSR)
and then jump to address 000h, where the interrupt service routine should be located. The service
routine is terminated by a return-from-interrupt instruction, which restores the program context and
causes the program to resume execution at the point where it was interrupted. In the SX18/20/28AC and SX18/20/28AC75 devices, there are two possible causes of an interrupt: • a rollover of the Real-Time Clock/Counter (RTCC) Table 6-1  Watchdog Timeout Settings     PS2:PS0
(with PSA=1) Watchdog Timer Output Divide-By Factor Typical Watchdog Timeout Period 000 1 0.016 sec 001 2 0.032 sec 010 4 0.064 sec 011 8 0.128 sec 100 16 0.256 sec 101 32 0.5 sec 110 64 1.0 sec 111 128 2.0 sec