© 2000 Scenix Semiconductor, Inc. All rights reserved. 149 SX User’s Manual Rev. 3.1 www.scenix.com Chapter 5 Input/Output Ports CMP_B: Comparator Register (MODE=18h) When you access the CMP_B register using the “mov !RB,W” instruction, the CPU does an exchange
between the contents of W and CMP_B. This feature lets you read the CMP_B register contents. Clear
bit 7 to enable operation of the comparator. Clear bit 6 to place the comparator result on the RB0 pin.
Bit 0 is a result flag that is set to 1 when the voltage on RB2 is greater than RB1, or cleared to 0
otherwise. (For more information using the comparator, see Chapter 7.) T2CNTB: Timer T2 Control B Register (MODE=16h) This register is present only in the SX48/52BD. You access it with the “mov !RC,W” instruction. The
seven low-order bits control the Timer T2 configuration as described in Section 8.4.4. The high-order
bit, called the PORTRD bit, selects the “port read” mode for all the I/O ports. Clear this bit to 0 to have
the device read data from the port I/O pins directly. Set this bit to 1 to have the device read data from
the port data registers. 5.3.5 Port Configuration Upon Reset Upon reset, all the port control registers are initialized to FFh. Thus, each pin is configured to operate
as a high-impedance input that senses TTL voltage levels, with no internal pullup resistor connected.
The MODE register is initialized to 0Fh for the SX18/20/28AC or to 1Fh for the SX48/52BD, which
allows immediate write access to the data direction registers with the “mov !rx,W” instruction. 5.3.6 Port Block Diagram Figure 5-1 is a block diagram showing the internal device hardware for one pin of Port B. This diagram will help you understand how the port operates and how to use it. Note that pin features related to the
Multi-Input  Wakeup/Interrupt  function  and  the  analog  comparator  function  are  not  shown  in  this
diagram. The boxes labeled RB Direction, PLP_B, LVL_B, and ST_B represent individual control bits within
the respective port control registers. The data registers and control registers are all mapped into the data
memory space at address 06h. The control registers are accessed with the “mov !RB,W” instruction,
with access controlled by the value in the MODE register; while the RB Data register bit is accessed
by ordinary file register instructions such as “mov $06,W”. The port pin is configured to operate as either a high-impedance input or an output, as determined by
the RB data register bit. When the pin is configured to operate as an input, the ST_B and LVL_B bits
determine the type of input buffer used. The ST_B bit either enables or disables the Schmitt trigger
input buffer. If the Schmitt trigger is disabled, the LVL_B bit selects either the TTL or CMOS buffer
for sensing the input voltage levels on the pin. When the device is configured to operate as an output, the bit in the RB data register is buffered and
placed on the output pin. Reading from the port data address returns the actual logic level on the pin
(in the default operating mode), even when the pin is configured to operate as an output. The  PLP_B  bit  either  connects  or  disconnects  the  internal  pullup  resistor.  If  the  pullup  resistor  is
disconnected, an external pullup will be required.