© 2000 Scenix Semiconductor, Inc. All rights reserved.
141
SX User’s Manual Rev. 3.1
www.scenix.com
Chapter 4 Clocking, Power Down, and Reset
4.5.3
Wakeup from the Power Down Mode
A wakeup from the power down mode (described in Section 4.3) causes a device reset. The SX18/20/
28AC devices have a fixed startup time of 18 ms when the wakeup reset occurs. The SX48/52BD de-
vices have a programmable startup time. A 2-bit field in the FUSEX register can be used to specify the
Delay Reset Timer (DRT) timeout period that results in an automatic wake-up from the power down
mode:
10 = 0.25 msec
11 = 18 msec (default)
00 = 60 msec
01 = 1 sec
For fast start-up from the power down mode, clear the SLEEPCLK bit and set the WDRT1:WDRT0
field to 10. This will keep the clock operating during the power down mode and allow a 0.06 msec
start-up delay.
Figure 4-7 Power-On Reset Timing, VDD Rise Time Too Slow
Figure 4-8 External Power-On MCLR Signal
Figure 4-9 Power-On Reset Timing, Separate MCLR Signal
VDD
MCLR
POR
drt_time_out
RESET
Tdrt
V1
VDD
R
C
MCLR
D
R1
VDD
MCLR
POR
drt_time_out
RESET
Tdrt
