© 2000 Scenix Semiconductor, Inc. All rights reserved. 133 SX User’s Manual Rev. 3.1 www.scenix.com Chapter 4 Clocking, Power Down, and Reset To use this mode, configure the device to operate in the XT, LP, or HS mode. It does not matter which
one of these modes you select. Then connect the clock signal to the OSC1 input and leave the OSC2
pin unconnected, as shown in Figure 4-3. 4.3 Power Down Mode In the SX power down mode, the device is shut down and the clock is stopped to all parts of the device.
The Watchdog timer, if enabled, continues to operate because it uses its own independent on-chip
oscillator. Upon wakeup from the power down mode, the device is reset and the program jumps to the
highest program address (7FFh or FFFh, depending on the SX device type). In the SX48/52B devices, the operating clock can be enabled or disabled during power down mode, by
using the SLEEPCLK bit of the FUSEX register. 4.3.1 Entering the Power Down Mode For the lowest possible power consumption in the power down state, disable the Watchdog timer. This
eliminates the power consumption of the Watchdog oscillator and counter. In that case, however, you
will not be able to use a Watchdog timeout to wake up the device. In addition, for SX48/52B devices,
the SLEEPCLOCK should be disabled during power down mode. The  device  enters  the  power  down  mode  upon  execution  of  the  “SLEEP”  instruction.  Program
execution stops and the device is powered down until a wakeup event occurs. If the Watchdog timer is enabled, the “SLEEP” instruction sets the TO (Watchdog Timeout) bit to 1
and clears the PD (Power Down) bit to 0 in the STATUS register. The Watchdog timer continues to
operate while the device is powered down. A Watchdog timeout will then wake up the device from the
power down state. Figure 4-3 External Clock Signal Connection        Externally
Generated Clock OSC1 OSC2 Open SX Device