© 2000 Scenix Semiconductor, Inc. All rights reserved. 139 SX User’s Manual Rev. 3.1 www.scenix.com Chapter 4 Clocking, Power Down, and Reset Table 4-1 lists the SX registers and shows the state of each register upon different resets. The column on the left lists the register names, and the first row shows the various types of reset operations. Each
entry in the table shows the state of the register just after the applicable reset operation. Table 4-1  Register States Upon Different Resets Register Power-On Wakeup Brown-out Watchdog Timeout MCLR W Undefined Unchanged Undefined Unchanged Unchanged OPTION FFh FFh FFh FFh FFh MODE (SX18/20/28AC)
MODE (SX48/52BD) 0Fh
1Fh 0Fh
1Fh 0Fh
1Fh 0Fh
1Fh 0Fh
1Fh RTCC (01h) Undefined Unchanged Undefined Unchanged Unchanged PC (02h) FFh FFh FFh FFh FFh STATUS (03h) Bits 0-2:
Undefined
Bits 3-4: 11
Bits 5-7: 000 Bits 0-2:
Undefined
Bits 3-4:
Unch.
Bits 5-7: 000 Bits 0-4:
Undefined
Bits 5-7: 000 Bits 0-2:
Unchanged
Bits 3-4:
(Note 1)
Bits 5-7: 000 Bits 0-2:
Unchanged
Bits 3-4:
(Note 2)
Bits 5-7: 000 FSR (04h) Undefined Bits 0-6:
Undefined
Bit 7: 1 Bits 0-6:
Undefined
Bit 7: 1 Bits 0-6:
Unchanged
Bit 7: 1 Bits 0-6:
Unchanged
Bit 7: 1 RA through RE
Direction FFh FFh FFh FFh FFh RA through RE Data Undefined Unchanged Undefined Unchanged Unchanged Other File Registers Undefined Unchanged Undefined Unchanged Unchanged CMP_B Bits 0, 6-7: 1
Bits 1-5:
Undefined Bits 0, 6-7: 1
Bits 1-5:
Undefined Bits 0, 6-7: 1
Bits 1-5:
Undefined Bits 0, 6-7: 1
Bits 1-5:
Undefined Bits 0, 6-7: 1
Bits 1-5:
Undefined WKPND_B Undefined Unchanged Undefined Unchanged Unchanged WKED_B FFh FFh FFh FFh FFh WKEN_B FFh FFh FFh FFh FFh ST_B through ST_E FFh FFh FFh FFh FFh LVL_A through LVL_E FFh FFh FFh FFh FFh PLP_A through PLP_E FFh FFh FFh FFh FFh Watchdog Counter Undefined Unchanged Undefined Unchanged Unchanged Timers T1 and T2
Free Running Timer/
Counter (SX48/52BD) 0001 0001 0001 0001 0001 Timers T1 and T2
Compare/Capture Register
(SX48/52BD) 0000 0000 0000 0000 0000 Timers T1 and T2
Control Registers
(SX48/52BD) 00 00 00 00 00 NOTE: 1. Watchdog reset during power down mode: 00 (bits TO, PD); Watchdog reset during Active mode: 01
(bits TO, PD) NOTE: 2. External reset during power down mode: 10 (bits TO, PD); External reset during Active mode: Un-
changed (bits TO, PD)