SX User’s Manual Rev. 3.1 120 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 3 Instruction Set 3.6.50    SLEEP Power Down Mode Operation: WDT = 00h STATUS(TO) = 1, STATUS(PD) = 0 stop oscillator Bits affected: none Opcode: 0000 0000 0011 Description: This instruction places the device in the power down mode. If the Watchdog timer
is enabled, the WDT register is cleared, the TO (timeout) bit in the STATUS regis-
ter is set to 1, and the PD (power down) bit in the STATUS register is cleared to 0. There are three types of events that can cause an exit from the power down mode:
a  Watchdog  timer  overflow,  a  transition  on  a  Multi-Input  Wakeup  pin,  or  an
external reset on the MCLR pin. For more information on the power down mode,
see Section 4.3. Cycles: 1 Example: sleep This  example  puts  the  device  into  the  power  down  mode  until  a  wakeup  event
occurs.