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SX20AC/SX28AC

10.2 Watchdog Timer

The watchdog logic consists of a Watchdog Timer which

shares the same 8-bit programmable prescaler with the

RTCC. The prescaler actually serves as a postscaler if

used in conjunction with the WDT, in contrast to its use as

a prescaler with the RTCC. The WDT is clocked by it's

own internal RC oscillator.
The Watchdog oscillator has a nominal operating fre-

quency of 16 kHz, or a period of 62.5 microseconds. At

this rate, the 8-bit counter counts from 00h to FFh in 16

milliseconds. In the default configuration (prescaler

assigned to WDT, with divide rate set to 1:128), the appli-

cation program needs to execute a "CLR !WDT" instruc-

tion at least once every 2 seconds to prevent a Watchdog

reset (if the WDTE bit in the FUSE register is set to 1).
See Table 4-2.

10.3 The Prescaler

The 8-bit prescaler may be assigned to either the RTCC

or the WDT through the PSA bit (bit 3 of the OPTION reg-

ister). Setting the PSA bit assigns the prescaler to the

WDT. If assigned to the WDT, the WDT clocks the pres-

caler and the prescaler divide rate is selected by the

PS0, PS1, and PS2 bits located in the OPTION register.

Clearing the PSA bit assigns the prescaler to the RTCC.

Once assigned to the RTCC, the prescaler clocks the

RTCC and the divide rate is selected by the PS0, PS1,

and PS2 bits in the OPTION register. The prescaler is not

mapped into the data memory, so run-time access is not

possible.
The prescaler cannot be assigned to both the RTCC and

WDT simultaneously.

Figure 10-1. RTCC and WDT Block Diagram

WDTE (from FUSE Word)

RTCC pin

MUX

8-Bit Prescaler

MUX (8 to 1)

8-Bits

WDT Time-out

Data Bus

WDT

MUX

RTCC

OSC

RST

RTE_ES

PSA

PS2
PS1
PS0

OPTION

RTCC Rollover

Interrupt

RTE_IE

RTW

RTCC

Interrupt

Enable

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