PIC Microcontroller Instruction Set
Comparison Matrix

		Processor Core
Opcode	Operation	12-Bit	14-Bit	16-Bit	16-Bit+
ADDLW	(W) + k --> (W)	--------	C DC Z	OV C DC Z	N OV C DC Z
ADDWF	(W) + (f) --> (dest)	C DC Z	C DC Z	OV C DC Z	N OV C DC Z
ADDWFC	(W) + (f) + C --> (dest)	--------	--------	OV C DC Z	N OV C DC Z
ANDLW	(W) AND k --> (W)	Z	Z	Z	N Z
ANDWF	(W) AND (f) --> (dest)	Z	Z	Z	N Z
BC	if C = 1, (PC) + 2 + 2n --> (PC)	--------	--------	--------	NONE
BCF	0 --> (f)	NONE	NONE	NONE	NONE
BN	if N = 1, (PC) + 2 + 2n --> (PC)	--------	--------	--------	NONE
BNC	if C = 0, (PC) + 2 + 2n --> (PC)	--------	--------	--------	NONE
BNN	if N = 0, (PC) + 2 + 2n --> (PC)	--------	--------	--------	NONE
BNOV	if OV = 0, (PC) + 2 + 2n --> (PC)	--------	--------	--------	NONE
BNZ	if Z = 0, (PC) + 2 + 2n --> (PC)	--------	--------	--------	NONE
BRA	(PC) + 2 + 2n --> (PC)	--------	--------	--------	NONE
BSF	1 --> (f)	NONE	NONE	NONE	NONE
BTFSC	skip if (f) = 0	NONE	NONE	NONE	NONE
BTFSS	skip if (f) = 1	NONE	NONE	NONE	NONE
BTG	!(f) --> (f)	--------	--------	NONE	NONE
BOV	if OV = 1, (PC) + 2 + 2n --> (PC)	--------	--------	--------	NONE
BZ	if Z = 1, (PC) + 2 + 2n --> (PC)	--------	--------	--------	NONE
CALL	Call Subroutine (operation is device specific)	NONE	NONE	NONE	NONE
CLRF	0x00 --> (f)	Z	Z	NONE	Z
CLRW	0x00 --> (W)	Z	Z	--------	--------
CLRWDT	0x00 --> WDT	TO PD	TO PD	TO PD	TO PD
COMF	!(f) --> (dest)	Z	Z	Z	N Z
CPFSEQ	(f) - (W), skip if (f) = (W)	--------	--------	NONE	NONE
CPFSGT	(f) - (W), skip if (f) > (W)	--------	--------	NONE	NONE
CPFSLT	(f) - (W), skip if (f) < (W)	--------	--------	NONE	NONE
DAW	Decimal Adjust W	--------	--------	C	C
DECF	(f) - 1 --> (dest)	Z	Z	OV C DC Z	N OV C DC Z
DECFSZ	(f) - 1 --> (dest) skip if 0	NONE	NONE	NONE	NONE
DCFSNZ	(f) - 1 --> (dest) skip if not 0	--------	--------	NONE	NONE
GOTO	Unconditional Branch (Operand is device specific)	NONE	NONE	NONE	NONE
INCF	(f) + 1--> (dest)	Z	Z	OV C DC Z	N OV C DC Z
INCFSZ	(f) + 1--> (dest) skip if 0	NONE	NONE	NONE	NONE
INFSNZ	(f) + 1 --> (dest) skip if not 0	--------	--------	NONE	NONE
IORLW	(W) OR k --> (W)	Z	Z	Z	N Z
IORWF	(W) OR (f) --> (dest)	Z	Z	Z	N Z
LFSR	k --> FSRf	--------	--------	--------	NONE
LCALL	Long Call Subroutine (operation is device specific)	--------	--------	NONE	--------
MOVF	(f) (dest)	Z	Z	--------	N Z
MOVFF	(f_s) --> (f_d)	--------	--------	--------	NONE
MOVFP	(f) --> (p)	--------	--------	NONE	--------
MOVLB	k --> (BSR<3:0>)	--------	--------	NONE	NONE
MOVLR	k --> (BSR<7:4>)	--------	--------	NONE	--------
MOVLW	k --> (W)	NONE	NONE	NONE	NONE
MOVPF	(p) --> (f)	--------	--------	Z	--------
MOVWF	(W) --> (f)	NONE	NONE	NONE	NONE
MULLW	(W) x k --> (PRODH:PRODL)	--------	--------	NONE	NONE
MULWF	(W) x (f) --> (PRODH:PRODL)	--------	--------	NONE	NONE
NEGW	!(W) + 1 --> (f); !(W) + 1 --> s	--------	--------	OV C DC Z	--------
NEGF	!(f) + 1 --> (f)	--------	--------	--------	N OV C DC Z
NOP	No operation	NONE	NONE	NONE	NONE
OPTION	(W) --> OPTION	NONE	NONE	--------	--------
POP	(TOS) --> bit bucket	--------	--------	--------	NONE
PUSH	(PC+2) --> TOS	--------	--------	--------	NONE
RCALL	(PC) + 2 --> TOS, (PC) + 2 + 2n --> (PC)	--------	--------	--------	NONE
RESET	Reset all registers and flags that are affected by a MCLR reset.	--------	--------	--------	All
RETFIE	Return from Interrupt (operation is device specific)	--------	NONE	GLINTD	GIE/GIEH PEIE/GIEL
RETLW	k --> (W, ) TOS --> PC	NONE	NONE	NONE	NONE
RETURN	Return from Subroutine (operation is device specific)	--------	NONE	NONE	NONE
RLCF/RLF	(f) --> (d); (f<7>) --> C; C --> (d<0>)	C (RLF)	C (RLF)	C (RLCF)	N C Z (RRCF)
RLNCF	(f) --> (d); (f<7>) --> (d<0>);	--------	--------	NONE	N Z
RRCF/RRF	(f) --> (d); (f<0>) --> C; C --> (d<7>)	C (RRF)	C (RRF)	C (RRCF)	N C Z (RRCF)
RRNCF	(f) --> (d); (f<0>) --> (d<7>);	--------	--------	NONE	N Z
SETF	0xFF --> (f)	--------	--------	NONE	NONE
SLEEP	Enter SLEEP Mode	TO PD GPWUF	TO PD	TO PD	TO PD
SUBFWB	(W) - (f) - !C --> (dest)	--------	--------	--------	N OV C DC Z
SUBLW	k - (W) --> (W)	--------	C DC Z	OV C DC Z	N OV C DC Z
SUBWF	(f) - (W) --> (dest)	C DC Z	C DC Z	OV C DC Z	N OV C DC Z
SUBWFB	(f) - (W) - !C --> (dest)	--------	--------	OV C DC Z	N OV C DC Z
SWAPF	(f<3:0>) --> (dest<7:4>); (f<7:4>) --> (dest<3:0>)	NONE	NONE	NONE	NONE
TABLRD	Table Read [17C] (operation is device specific)	--------	--------	NONE	--------
TABLWT	Table Write [17C] (operation is device specific)	--------	--------	NONE	--------
TBLRD	Table Read [18C] (operation is device specific)	--------	--------	--------	NONE
TBLWT	Table Write [18C] (operation is device specific)	--------	--------	--------	NONE
TLRD	Table Latch Read [17C] (operation is device specific)	--------	--------	NONE	--------
TLWT	Table Latch Read [17C] (operation is device specific)	--------	--------	NONE	--------
TRIS	(W) --> TRIS Register f	NONE	NONE	--------	--------
TSTFSZ	skip if (f) = 0	--------	--------	NONE	NONE
XORLW	(W) XOR k --> (W)	Z	Z	Z	N Z
XORWF	(W) XOR (f) --> (dest)	Z	Z	Z	N Z

Notes:

Instructions shown in grey are obsolete and Microchip recommends that they not be used in order to maintain compatibility with future PIC versions.
Instructions that have a "--------" under the Processor Core column are not valid instructions for that core.
Descriptions shown under the "Operation" column are intended to describe briefly the corresponding instruction's function. In some cases the operation of an instruction varies from family to family. Consult the specific PIC processor's data sheet for more information.
Some instructions shown above perform operations on status and other control flags which are device specific. Consult the specific PIC processor's data sheet for more information.

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