" Database for National Semiconductor GAL 16v8; AJF September 1990 "

22 20 32	" <# of pins> <physical # of pins> <# of inputs to AND array> "

" Syntax:   <pintype> <true fuse addr> <false fuse addr> <f/b source> <o/p type>

  Pin Types:
     CLOCK     = dedicated clock
     CONTROL   = dedicated control pin, e.g. tristate enable
     CLK_INPUT = clock and input
     INPUT     = input
     OUTPUT    = output
     BREG      = buried registers
     IO	       = input or output; i.e., with feedback
     VCC, GND  = power, ground pins

  Feedback source indicates where feedback is being taken:
  e.g.; in a registered part, feeback can come from HIGH or LOW Q output of the register.
  Feedback Source: 0 = HIGH_FDBK
		 : 1 = LOW_FDBK
		 : 2 = NO_FDBK
		 : 3 = CORRECT_FDBK

  Output Types:
     0	= programmable
     1	= active LOW
     2	= active HIGH

  Architecture fuses marked by # with choices marked by + "


1  CLOCK @

2  INPUT 0 1 2 0
   0 0 0 0
   # COMBINATORIAL -1
   @

3  INPUT 4 5 2 0
   0 0 0 0
   # COMBINATORIAL -1
   @

4  INPUT 8 9 2 0
   0 0 0 0
   # COMBINATORIAL -1
   @

5  INPUT 12 13 2 0
   0 0 0 0
   # COMBINATORIAL -1
   @

6  INPUT 16 17 2 0
   0 0 0 0
   # COMBINATORIAL -1
   @

7  INPUT 20 21 2 0
   0 0 0 0
   # COMBINATORIAL -1
   @

8  INPUT 24 25 2 0
   0 0 0 0
   # COMBINATORIAL -1
   @

9  INPUT 28 29 2 0
   0 0 0 0
   # COMBINATORIAL -1
   @

10 GND @

11 CONTROL @

12 IO 30 31 0 0
   7 1824		" 7 product terms (PT), starting at link address 1824 "
   1 1792		" 1 tristate/enable PT, starting at link address 1792 "
   0 0			" no sync preset PTs;  no async reset PTs "
   # XOR_0 2055 0 + XOR_1 2055 1
   # AC1_0 2127 0 + AC1_1 2127 1
   # SYN_0 2192 0
   # AC0_1 2193 1
   @

13 IO 26 27 0 0
   7 1568
   1 1536
   0 0
   # XOR_0 2054 0 + XOR_1 2054 1
   # AC1_0 2126 0 + AC1_1 2126 1
   # SYN_0 2192 0
   # AC0_1 2193 1
   @

14 IO 22 23 0 0
   7 1312
   1 1280
   0 0
   # XOR_0 2053 0 + XOR_1 2053 1
   # AC1_0 2125 0 + AC1_1 2125 1
   # SYN_0 2192 0
   # AC0_1 2193 1
   @

15 IO 18 19 0 0
   7 1056
   1 1024
   0 0
   # XOR_0 2052 0 + XOR_1 2052 1
   # AC1_0 2124 0 + AC1_1 2124 1
   # SYN_0 2192 0
   # AC0_1 2193 1
   @

16 IO 14 15 0 0
   7 800
   1 768
   0 0
   # XOR_0 2051 0 + XOR_1 2051 1
   # AC1_0 2123 0 + AC1_1 2123 1
   # SYN_0 2192 0
   # AC0_1 2193 1
   @

17 IO 10 11 0 0
   7 544
   1 512
   0 0
   # XOR_0 2050 0 + XOR_1 2050 1
   # AC1_0 2122 0 + AC1_1 2122 1
   # SYN_0 2192 0
   # AC0_1 2193 1
   @

18 IO 6 7 0 0
   7 288
   1 256
   0 0
   # XOR_0 2049 0 + XOR_1 2049 1
   # AC1_0 2121 0 + AC1_1 2121 1
   # SYN_0 2192 0
   # AC0_1 2193 1
   @

19 IO 2 3 0 0
   7 32
   1 0
   0 0
   # XOR_0 2048 0 + XOR_1 2048 1
   # AC1_0 2120 0 + AC1_1 2120 1
   # SYN_0 2192 0
   # AC0_1 2193 1
   @

20 VCC @

21 OUTPUT 0 0 0 0	" pseudo-pin; must say ENABLE(pin21) to set PDT bits to zero "
   0			" no PTs for this pseudo-pin                                 "
   1 2128		" 1 enable PT (32 bits), starting at fuse address 2128       "
   0 0
   @

22 OUTPUT 0 0 0 0
   0
   1 2160
   0 0
   @

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