There are thee general groups of instuctions:
Instruction Formats
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Description |
Op-code |
Ad | Bw | Double Operand Note As is 2 bits, Ad is 1 | |||||||||||||
| 0 | 0 | 0 | 1 | 0 | 0 | Op-code | Bw | Ad |
D-Reg |
Single Operand Note Ad is now 2 bits | ||||||
| 0 | 0 | 1 | Condition | 10 bit PC Offset |
Jumps | |||||||||||
In Single Operand instructions, Ad is the two bit value indicating the
Destination Addressing Mode and is decoded as per this table, in Double Operand
instructions As is the 2 bit Source Addressing Mode value and Ad is a single
bit. This single bit selects between Direct or Indexed addressing (again
using an immediate number stored after the instruction). Of course, Indirect
is easy to fake with a 0 offset in the Indexed address. In the case that
both source and destination addresses are Indexed, the immediate value for
the source is stored directly after the instruction, followed by the one
for the destination address.
| Ax | Name | Source | Syntax | Description |
| 00 | Direct | Register | Rn | The actual value stored in the register indicated by S-Reg |
| 01 | Indexed | Memory pointed to by Register + Immediate Number |
n(Rn) | An immediate 16 bit value (stored in the next program word after the
instruction) is added to the value in the register. If the register is R0 (the PC) then we have PC relative addressing. This is how labels are referenced. The assembler will translate &lable into lable(R0) |
| 10 | Indirect | Memory pointed to by Register | @Rn | The value in the register is used to index memory and return the value
at that addres in memory. In a Double Operand instruction, since there is no Indirect mode for the destination (Ad is only 1 bit, remember), the assembler will translate a destination of @Rn into an Indexed mode reference to 0(Rn) |
| 11 | Increment | Memory pointed to by Register (Increment Register) |
@Rn+ | Just like Indirect but then the register is incremented by 1 for byte
or 2 for word depending on Bw. Note: the exception is when the register
is the Stack Pointer: Then it is always incremented by 2. When the register is PC, the source is an immediate value stored after the instruction which will be skipped by the increment! Clever huh? The syntax for that is just #n and the assembler will translate it into @R0+ and put the value of n in the word after the instruction. The source register is incremented before the destination is computed so if the same register is used as the destination, the source with be based on the original value and the destination on the incremented value. In a Double Operand instruction, the destination can not be post incremented (Ad is only 1 bit!), only the source. In a Single Operand instuction, Ad is 2 bits, and the destination can be incremented just fine. |
When r2 (the status register) or r3 (the zero register) are specified, the addressing mode bits are decoded specially:
| As | S-Reg | Value | Description |
| 00 Direct | 0010 R2 | R2 | Normal access. The actual value of the Status Register is read. |
| 01 Indexed | 0010 " | &<location> | Absolute addressing. The extension word is used as the address directly. |
| 10 Indirect | 0010 " | #4 | |
| 11 Increment | 0010 " | #8 | |
| 00 Direct | 0011 R3 | #0 | See why R3 is called the Zero Register? Its direct value is el-zippo. Isn't really a register is it? |
| 01 Indexed | 0011 " | #1 | But when you use it as a source in an Indexed operation, it becomes a 1 |
| 10 Indirect | 0011 " | #2 | And as an Inderect source, it looks like a 2 |
| 11 Increment | 0011 " | # -1 | And if you try to Increment it, all its bits are set! |
Memory aid: R3 returns a sign extended version of the As mode.
Instructions
| Mnemonic | S-Reg, D-Reg |
Operation | Status Bits |
||||
| V | N | Z | C | ||||
| MOV(.B) | src,dst | src » dst | - | - | - | - | |
| ADD(.B) | src,dst | src + dst » dst | * | * | * | * | |
| ADDC(.B) | src,dst | src + dst + C » dst | * | * | * | * | |
| SUB(.B) | src,dst | dst + .not.src + 1 » dst | * | * | * | * | |
| SUBC(.B) | src,dst | dst + .not.src + C » dst | * | * | * | * | |
| CMP(.B) | src,dst | dst - src | * | * | * | * | |
| DADD(.B) | src,dst | src + dst + C » dst (decimally) | * | * | * | * | |
| BIT(.B) | src,dst | src .and. dst | 0 | * | * | * | |
| BIC(.B) | src,dst | .not.src .and. dst » dst | - | - | - | - | |
| BIS(.B) | src,dst | src .or. dst » dst | - | - | - | - | |
| XOR(.B) | src,dst | src .xor. dst » dst | * | * | * | * | |
| AND(.B) | src,dst | src .and. dst » dst | 0 | * | * | * | |
Emulated Group
See:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |