SX User’s Manual Rev. 3.1 78 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 3 Instruction Set 3.6.10    CLR !WDT Clear Watchdog Timer Operation: Clears Watchdog timer counter and prescaler counter Bits affected: Z, TO, PD Opcode: 0000 011f ffff Description: This  instruction  clears  the  Watchdog  Timer  counter  to  zero.  It  also  clears  the
Watchdog prescaler register to zero, and sets the Z, TO, and PD bits to 1 (the Zero,
Watchdog Timeout, and Power Down bits in the STATUS register). If  the  Watchdog  circuit  is  enabled,  the  application  software  must  execute  this
instruction periodically in order to prevent a Watchdog reset. Cycles: 1 Example: clr !WDT This  example  clears  the  Watchdog  Timer  counter  and  the  Watchdog  prescaler
register to zero; and sets the Z, TO, and PD bits.