SX User’s Manual Rev. 3.1 52 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 2 Architecture Table 2-11  FUSE Word Configuration Bits for SX48/52BD Option Bits Description SYNC Synchronous Input Mode Enable. Set to 1 to disable or clear to 0 to enable.This
bit allows an input signal to be synchronized with internal clock through two
internal flip-flops. If enabled, port data must be read more than 2 cycles after a
change to the input level mode or Schmitt trigger mode.
0 = enabled
1 = disabled IRC Internal RC oscillator enable:
0 = enabled - OSC1 is pulled low by a weak pullup, OSC2 is pulled high by a
weak pullup
1 = disabled - OSC1 and OSC2 behave according to FOSC2: FOSC0 DIV1: DIV0 Internal RC oscillator divider (if IRC = 0):
00b = 4 MHz
10b = 1 MHz
01b = 125 KHz
11b = 31.25 KHz IFBD Internal crystal/resonator oscillator feedback resistor (10 M):
0 = Internal feedback resistor disable (external feedback required for crystal/reso- nator operation) 1 = Internal feedback resistor enabled (valid only when IRC = 1) XTLBUF_EN Crystal Buffer enable (disable when not using a resonator/crystal to reduce Idd):
0 = Crystal/resonator Buffer disabled
1 = Crystal/resonator Buffer enabled CP Code protect enable:
0 = enabled (FUSE, code, and ID memories read back as scrambled data)
1 = disabled (FUSE, code, and ID memories can be read normally)