SX User’s Manual Rev. 3.1 40 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 2 Architecture 2.5.2 Pipeline Delays Any  instruction  or  interrupt  condition  that  alters  the  normal  program  flow  will  take  at  least  one
additional instruction cycle. For example, when a test-and-skip instruction is executed and the tested
condition is true, the next instruction in the program is skipped. The next instruction occupies space
and takes up time in the pipeline whether or not it is skipped. As a result, a skipped instruction causes
a delay of one instruction cycle when a skip occurs. The test-and-skip instruction is described as taking
one cycle if the tested condition is false or two cycles if the tested condition is true. The  call,  jump,  and  return-from-interrupt  instructions  reload  the  program  counter  and  cause  the
program to jump to an entirely new location in program memory. As a result, the instructions in the
pipeline are discarded, causing a multi-cycle delay in program execution. Each call, jump, and return-
from-interrupt instruction takes two, three, or four cycles for execution, depending on the specific
instruction and the device clocking mode. For details, see the instruction descriptions in Chapter 3. For the same reason, the triggering of an interrupt causes a pipeline delay. For an RTCC interrupt, the
delay is three cycles. For a  Multi-Input Wakeup interrupt, the  delay is five cycles (two cycles  for
interrupt synchronization and a three-cycles pipeline delay). 2.5.3 Read-Modify-Write Considerations A “read-modify-write” instruction is an instruction that operates by reading a register, modifying the
value, and writing the result back to the register. Any instruction that writes a new value to a register
that depends on the existing value is a read-modify-write instruction. Some examples are “clrb fr.bit”
(clear  bit),  “setb  fr.bit”  (set  bit),  “add  fr,w”  (add  W  to  file  register),  and  “dec  fr”  (decrement  file
register). The “set bit” instruction, for example, does not simply set one bit and ignore the others.
Instead, it reads the whole register, sets the specified bit to “1”, and writes the whole result back to the
register. When  you  use  successive  read-modify-write  instructions  on  a  port  data  register,  you  might  get
unexpected results at very high clock rates (such as 50/75 MHz). When you write to an I/O port, you
write to the port data register; but when you read a port, you read the actual voltage on the I/O port pin
(in the default operating mode). There is a slight delay from the time that the data port is written and
the time that the output voltage changes to the programmed level. When you use two successive read-modify-write instructions on the same I/O port, the “write” part of
one  instruction  might  not  occur  soon  enough  before  the  “read”  part  of  the  very  next  instruction,
resulting in getting “old” data for the second instruction. (Remember that successive instructions are
executed in parallel, one behind the next in the pipeline.) To ensure predictable results, avoid using two successive read-modify-write instructions that access
the  same  port  data  register.  For  example,  you  can  insert  a  “nop”  instruction  between  two  such
instructions in the program.