© 2000 Scenix Semiconductor, Inc. All rights reserved. 37 SX User’s Manual Rev. 3.1 www.scenix.com Chapter 2 Architecture 2.4.9 OPTION (Device Option Register) The  OPTION register  sets several device  configuration options,  mostly related to  operation  of  the
Real-Time  Clock/Counter.  The  format  of  the  register  is  shown  below.  Upon  reset,  all  bits  in  this
register are set to 1. NOTE: For SX18/20/28AC and SX18/20/28AC75 devices, the upper 2 bits (RTW and RTE-IE)
of the OPTION register are available only when the OPTIONS bit in the FUSEX register
is cleared. For SX48/52BD devices, these bits are always available. RTW Bit: RTCC or W at address 01h For SX18/20/28AC and SX18/20/28AC75 devices, clear the RTW bit to 0 to make W available as a
memory-mapped register at address 01h. Set the RTW bit to 1 for the default register configuration,
with  RTCC  at  address  01h.  Before  you  can  clear  the  RTW  bit,  the  option  must  be  enabled  by
programming the OPTIONX bit to 0 in the FUSEX word in the program memory. For SX48/52BD devices, the RTW function is always available. RTE_IE Bit: RTCC Rollover Interrupt Enable Clear the RTE_IE bit to 0 to enable the interrupt that occurs upon rollover of the RTCC counter, or set
this bit to 1 to disable the interrupt. Before you can clear the RTE_IE bit, the option must be enabled
by programming the OPTIONX bit (SX18/20/28AC and SX18/20/28AC75 devices only) to 0 in the
FUSEX word register. For SX48/52BD devices, the RTE-IW function is always available. RTS Bit: RTCC Trigger Selection Clear the RTS bit to 0 to have the RTCC counter incremented automatically with each instruction cycle
(or a specified number of instruction cycles). This mode can be used to implement a real-time clock.
Set the RTS bit to 1 to have the RTCC counter incremented once each time a transition is detected on
the RTCC input pin (or a specified number of transitions). This mode can be used as an external event
counter. RTE_ES: RTCC Input Edge Select When the RTCC counter is configured to count transitions received on the RTCC pin (when RTS=1),
the RTCC bit specifies the type of signal edges detected on the RTCC pin. Set RTE_ES to 1 to detect
high-to-low transitions on the RTCC pin. Clear RTE_ES to 0 to detect low-to-high transitions on the
RTCC pin. RTW RTE_IE RTS RTE_ES PSA PS2 PS1 PS0 Bit 7 Bit 0