SX User’s Manual Rev. 3.1 166 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 8 Multi-Function Timers The CPU can access the R1, R2, and Capture registers by using the “mov !RB,W” instruction for T1
or the “mov !RC,W” instruction for T2. The other timer registers are not directly accessible. You can configure the timer to generate an interrupt upon overflow from FFFFh to 0000h, upon a
match between the counter value and a programmed comparison value, or upon the occurrence of a
valid capture signal on either of two capture inputs. 8.2 Timer Operating Modes Each timer can be configured to operate in one of the following modes: • Pulse Width Modulation (PWM) mode • Software Timer mode • External Event mode • Capture/Compare mode 8.2.1 PWM Mode In  the  Pulse  Width  Modulation  (PWM)  mode,  the  timer  generates  an  output  signal  having  a
programmable  frequency  and  duty  cycle.  To  use  this  mode,  you  load  the  two  16-bit  comparison
registers, R1 and R2, with the number of timer clock cycles that you want the output signal to be high
and low. The timer starts from zero and counts up until it reaches the value in R1. At that point, it generates an
interrupt (if enabled), toggles the output signal, and starts counting from zero again. The second time,
it counts up until it reaches the value in R2. At that point, it again generates an interrupt (if enabled),
toggles the output signal, and starts counting from zero again. This process is repeated continuously,
alternating between R1 and R2 to obtain the value at which to toggle the output signal and return the
counter to zero. The values of R1 and R2 establish the duty cycle and frequency of the output signal.
If R1 and R2 contain the same value, the resulting output signal is a square wave. In the PWM mode, the timer is clocked by the on-chip system clock divided by an 8-bit prescaler value.
The divide-by factor can be set to any power-of-2 from 1 to 256. Thus, the period of the timer clock
can be set from 1 to 256 times the system clock period. 8.2.2 Software Timer Mode The Software Timer mode is the same as the PWM mode, except that the timer does not toggle the
output signal. Instead, the application program takes action in response to the interrupts generated upon
each match between the counter and the contents of the active comparison value in either R1 or R2.
The software can determine the cause of each interrupt by checking the timer interrupt pending flags.
There is a different flag bit associated with each type of event (R1 match, R2 match, or overflow).