SX User’s Manual Rev. 3.1 12 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 1 Overview CPU Features •   Compact instruction set
•   All instructions are single cycle except branch
•   Eight-level push/pop hardware stack for subroutine linkage
•   Fast table lookup capability through run-time readable code (IREAD instruction)
•   Predictable program execution flow for hard real-time applications Fast and Deterministic Interrupt •   Jitter-free 3-cycle internal interrupt response
•   Hardware context save/restore of key resources such as PC, W, STATUS, and FSR within the 3- cycle interrupt response time •   External wakeup/interrupt capability on Port B (8 pins) Flexible I/O •   All pins individually programmable as I/O
•   Inputs are TTL or CMOS level selectable
•   All pins have selectable internal pull-ups
•   Selectable Schmitt Trigger inputs on Ports B, C, D, and E
•   All outputs capable of sourcing/sinking 30 mA
•   Port A outputs have symmetrical drive
•   Analog comparator support on Port B (RB0 OUT, RB1 IN-, RB2 IN+)
•   I/O operation synchronous to the oscillator clock (user selectable) Hardware Peripheral Features •   Two 16-bit timers with 8-bit prescalers supporting (SX48/52BD devices only): –   Software Timer mode
–   PWM mode
–   Simultaneous PWM/Capture mode
–   External Event mode •   One 8-bit Real Time Clock/Counter (RTCC) with programable 8-bit prescaler
•   Watchdog Timer (shares the RTCC prescaler)
•   Analog comparator
•   Brown-out detector
•   Multi-Input Wakeup logic on 8 pins
•   Internal RC oscillator with configurable rate from 31.25 KHz to 4 MHz
•   Power-On-Reset Packages •   SX18/2028AC and SX18/20/28AC75: 18pin SO/DIP, 20-pin SSOP, 28-pin SO/DIP
•   SX48/52BD family: 48-pin Tiny PQFP, and 52-pin PQFP
•   SX52BD75: 52-pin PQFP
•   SX52BD100: 52-pin PQFP