SX User’s Manual Rev. 3.1 11 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 1 Overview 1.1     Introduction The  Scenix  SX  family  of  configurable  communications  controllers  are  fabricated  in  an  advanced
CMOS process technology. The advanced process, combined with a RISC-based architecture, allows
high-speed computation, flexible I/O control, and efficient data manipulation. Throughput is enhanced
by operating the device at frequencies up to 100 MHz and by optimizing the instruction set to include
mostly   single-cycle   instructions.   In   addition,  the  SX   architecture   is   deterministic   and   totally
reprogramable. The unique combination of these characteristics enables the device to implement real-
time functions as software modules (Virtual Peripheral^TM) to replace traditional hardware functions. On-chip core functions include a general-purpose 8-bit timer with prescaler, an analog comparator, a
brown-out detector, a watchdog timer, a power-save mode with multi-source wakeup capability, an
internal R/C oscillator, user-selectable clock modes, and high-current outputs. Additional features are
provided by individual members of the SX family according to the system requirements, such as PWM
timers and additional I/O ports. 1.2 Key Features 50/75/100 MIPS Performance •   DC - 100 MHz operation
•   10 ns instruction cycle, 30 ns internal interrupt response at 100 MHz
•   1 instruction per clock (branches 3) EE/FLASH Program Memory and SRAM Data Memory •   Access time of < 10 ns provides single cycle access
•   EE/Flash rated for > 10,000 rewrite cycles
•   SX18/20/28AC and SX18/20/28AC75: –   2048 words of EE/Flash program memory
–   136 bytes of SRAM data memory •   SX48/52BD: –   4096 words of EE/Flash program memory
–   262 bytes of SRAM data memory