SX User’s Manual Rev. 3.1 60 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 3 Instruction Set Table 3-1  Logic Instructions Syntax Description Cycles Opcode Bits Comp.     Turbo AND fr, W AND of fr and W into fr 1 1 0001 011f ffff Z AND W, fr AND of W and fr into W 1 1 0001 010f ffff Z AND W,#lit AND of W and Literal into W 1 1 1110 kkkk kkkk Z NOT fr Complement of fr into fr 1 1 0010 011f ffff Z OR fr,W OR of fr and W into fr 1 1 0001 001f ffff Z OR W,fr OR of W and fr into fr 1 1 0001 000f ffff Z OR W,#lit OR of W and Literal into W 1 1 1101 kkkk kkkk Z XOR fr,W XOR of fr and W into fr 1 1 0001 101f ffff Z XOR W,fr XOR of W and fr into W 1 1 0001 100f ffff Z XOR W,#lit XOR of W and Literal into W 1 1 1111 kkkk kkkk Z Table 3-2  Arithmetic and Shift Instructions (Sheet 1 of 2) Syntax Description Cycles Opcode Bits Comp. Turbo ADD fr,W Add W to fr 1 1 0001 111f ffff    C, DC, Z ADD W,fr Add fr to W 1 1 0001 110f ffff    C, DC, Z CLR fr Clear fr 1 1 0000 011f ffff Z CLR W Clear W 1 1 0000 0100 0000 Z CLR !WDT Clear Watchdog Timer 1 1 0000 0000 0100 TO, PD DEC fr Decrement fr 1 1 0000 111f ffff Z DECSZ fr Decrement fr and Skip if
Zero    1 or
2 (skip)    1 or
2 (skip) 0010 111f ffff none INC fr Increment fr 1 1 0010 101f ffff Z INCSZ fr Increment fr and Skip if
Zero    1 or
2 (skip)    1 or
2 (skip) 0011 111f ffff none RL fr Rotate fr Left through Carry 1 1 0011 011f ffff C