SX User’s Manual Rev. 3.1 55 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 3 Instruction Set 3.1     Introduction The  Scenix  SX  configurable  communications  controllers  use  a  RISC  (Reduced  Instruction  Set
Computer) architecture. In this type of architecture, the instruction set is limited in complexity and
diversity, but the instructions can be executed very fast, typically at a rate of one instruction per clock
cycle. High performance is achieved by executing many simple instructions very fast. The instruction set consists entirely of single-word (12-bit) instructions, most of which can be executed
at a rate of one instruction per clock cycle, for a total throughput of up to 50 MIPS (million instructions
per second) when the device operates with a 50 MHz clock. The only common instructions that take
more  than one clock  cycle to execute are those that control program flow, such as call and  return
instructions, and test-and-skip instructions that result in a skip. 3.2 Instruction Operands An SX program consists of a sequence of instructions stored in the device program memory. Each
instruction,  when  executed,  changes  the  data  contained  in  one  or  more  device  registers.  All  data
registers are eight bits wide. Most of the device registers are memory-mapped. Each memory-mapped register occupies an address
in the data memory address space, and can be accessed by the “mov” instructions of the SX instruction
set. An instruction refers to a memory-mapped register by specifying a 5-bit “fr” (file register) value
in the instruction. Multiple sets or “banks” of registers are available, as specified by the File Select
Register (FSR). For more information on register addressing modes, see Section 2.3. The W (Working) register is used in many of the instructions but is not memory-mapped. It is often
used as the source or destination of an operation. The letter “W” represents this register in the syntax
of the assembly language. There are several dedicated-purpose registers and many general-purpose registers in the data memory
address  space,  organized  as  described  in  Chapter  2.  The  exact  number  of  registers  and  their
organization depend on the specific SX device type. The source data for an operation can be provided by the instruction opcode itself rather than a register.
An  operand  provided  this  way  is  called  an  “immediate”  operand.  In  the  syntax  of  the  assembly
language, the “number” or “pound” character (#) indicates an immediate value. Here is one example: mov W,#$0F ;move immediate value 0Fh into W