SX User’s Manual Rev. 3.1 50 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 2 Architecture WDTE Watchdog timer enable. Set to 1 to enable the Watchdog timer. Clear to 0 to dis-
able the Watchdog timer. FOSC1:
FOSC0 External Oscillator Configuration. This combination of three register bits sets up
the device to operate with a particular type of external oscillator when the device
is configured to operate with an external oscillator (IRC = 1). Note that bit 5, the
DIV0/FOSC2 bit, operates as DIV0 with IRC=0, or as FOSC2 with IRC=1. The
type of external oscillator is determined by FOSC2:FOSC0 as follows:
000 = LP1 – low-power crystal (32 KHz)
001 = LP2 – low-power crystal/resonator (32 KHz to 1 MHz)
010 = XT1 – low-power crystal/resonator (32 KHz to 10 MHz)
011 = XT2 – normal crystal/resonator (1 MHz to 24 MHz)
100 = HS1 – normal crystal/resonator (1 MHZ to 50 MHz)
101 = HS2 – normal crystal/resonator (1 MHZ to 50 MHz)
110 = HS3 – normal crystal/resonator (1 MHZ to 50 MHz)
111 = External RC (OSC2 is pulled high with a weak pullup (no CLKOUT out-
put)
Note: The frequency ranges have not been characterized. These are target values. Table 2-9  FUSE Word Register Configuration Bits for SX18/20/28AC (Sheet 2 of 2) Option Bits Description