© 2000 Scenix Semiconductor, Inc. All rights reserved. 49 SX User’s Manual Rev. 3.1 www.scenix.com Chapter 2 Architecture Table 2-9  FUSE Word Register Configuration Bits for SX18/20/28AC (Sheet 1 of 2) Option Bits Description TURBO Turbo Mode. Set to 1 for “compatible” mode, in which the instruction rate oper-
ates at one-fourth the oscillator clock rate. Set to 0 for the turbo mode, in which
the instruction rate is equal to the oscillator clock rate. SYNC Synchronous Input Mode (for turbo mode operation). Set to 1 to disable or clear
to 0 to enable.This bit allows an input signal to be synchronized with internal
clock through two internal flip-flops. IRC Internal RC Oscillator. Set to 1 to disable the internal oscillator and have the
OSC1 and OSC2 pins operate as defined by the FOSC2:FOSC0 bits. Clear to 0 to
enable the internal oscillator, and to have the OSC1 pin pulled low by weak pull-
up and the OSC2 pin pulled high by weak pullup. DIV2:DIV0 Internal RC Oscillator Divider. This field sets the divide-by factor for generating
the instruction clock from the internal oscillator when the internal oscillator is
enabled (IRC = 0). The nominal instruction rate is determined by DIV1:DIV0 as
follows:
00 = 4 MHz
01 = 1 MHz
10 = 128 KHz
11 = 32 KHz IFBD Internal Feedback Disable. If IRC = 1, and IFBD = 1, the crystal/resonator oscil-
lator can rely on the internal feedback resistor between the OSC1 and OSC2 pins.
If IFBD = 0, an external feedback resistor is required between the OSC1 and
OSC2 pins. CP Code Protection. Set to 1 for no code protection. Clear to 0 for code protection.
With code protection, the program code and configuration registers read back as
scrambled data. This prevents reverse-engineering of your proprietary code and
configuration options.