SX User’s Manual Rev. 3.1 34 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 2 Architecture In the default configuration, the carry bit is not used as an input to addition and subtraction operations.
In that case, the carry bit can still be added or subtracted explicitly by using a separate “test carry bit
and skip” instruction in conjunction with an “increment” or “decrement” instruction. For rotate (RR or RL) instructions, the carry bit is loaded with the bit 0 or bit 7 respectively. 2.4.6 FSR (File Select Register) The FSR register (address 04h) is the File Select Register used to specify the bank number for semi-
direct addressing of file registers, or the full 8-bit address for indirect addressing of file registers. The
file registers are addressed as follows: • For semi-direct addressing, the high-order bits of FSR specify the bank number, and the instruc-
tion opcode specifies the register within the selected bank. The low-order bits of FSR are ignored
in this addressing mode. • For indirect addressing, the FSR register specifies the full 8-bit address of the register being ac-
cessed. To invoke this mode, the instruction specifies address 00h (INDF) as the source or des- tination of the operation. For more information on using the FSR register for addressing the data registers, see Section 2.3. 2.4.7 RA through RE (Port Data Registers) The RA, RB, RC, RD, and RE registers (addresses 05h, 06h, 07h, 08h, and 09h) are the I/O port data
registers for Port A through Port E. When a port is configured to operate as an output, writing to its
port data register sets the output values of the port pins. In the default operating mode, reading from
one  of  these  register  locations  reads  the  port  pins  directly  (not  necessarily  returning  the  values
contained in the port data register). For the SX48/52BD, a control bit called PORTRD in the T2CNT2 register determines how the device
reads data from its I/O ports. Set this bit to 1 to have the device read data directly from the port I/O
pins (the default operating mode). Clear this bit to 0 to have the device read data from the port data
registers. For detailed information on configuring and using the I/O ports, see Chapter 5. 2.4.8 Port Control Registers and MODE Register The MODE register controls access to the port control registers for subsequent uses of the “MOV
!rx,W” instruction. For example, there are three registers for controlling Port A: the RA Direction
register, the PLP_A (pullup enable A) register, and the LVL_A (level selection A) register. One of
these three registers is accessed by the “MOV !RA,W” instruction, depending on the value contained
in the MODE register. For the SX48/52BD, use MODE values of 0Fh, 0Eh, or 0Dh, respectively to
read the RA Direction, PLP_A, and LVL_A registers; or 1Fh, 1Eh, or 1Dh, respectively to write these
same registers. On the SX18/20/28AC and SX18/20/28AC75 devices, the port control registers are
write-only registers, and bit 4 of the MODE register is a “don’t care” bit.