© 2000 Scenix Semiconductor, Inc. All rights reserved. 25 SX User’s Manual Rev. 3.1 www.scenix.com Chapter 2 Architecture For  the  first  16  addresses  that  can  be  specified  in  an  instruction  (00h  through  0Fh),  the  same  16
registers  are  accessed,  irrespective  of  the  bank  setting.  Therefore,  these  16  “global”  registers  are
always accessible. The first eight are dedicated-purpose registers (INDF, RTCC, PC, and so on), and
the next eight are general-purpose registers. In Table 2-1, these registers are shown shaded in Bank 1
through Bank 7 to indicate that they are the same registers as in Bank 0. For the upper 16 addresses that can be specified in an instruction (10h through 1Fh), a different set of
registers is accessed in each bank. This allows as many as 128 different registers to be accessed in this
memory range, although only 16 are accessible at any given time. The total number of general-purpose registers is 24 in Bank 0 (from 08h to 1Fh) and 16 in each of the
remaining seven banks (from 10h to 1Fh in each bank), for a total of 136 registers. In the SX18AC/
SX18AC75 and SX20AC/SX20AC75 devices, an additional general-purpose register is available at
address 08h because there is no Port C register occupying that address. There  are two  addressing modes for  the SX18/20/28AC  and  SX18/20/28AC75 devices,  called  the
indirect and direct modes. The addressing mode used for register access depends on the 5-bit “fr” value
used in the instruction: • indirect mode: fr = 00h • direct mode: fr = 01h through 1Fh For indirect addressing (fr=00), the File Select Register (FSR) specifies the register to be accessed.
FSR is an 8-bit, memory-mapped register (at address 04h) which serves as an 8-bit pointer into data
memory for indirect addressing. For direct addressing with bit 4 of “fr” equal to 0 (fr=01-0F), Bank 0 is accessed and the value of “fr”
itself specifies the register to be accessed. In this case, a “global” register in Bank 0 is accessed (01h
through 0Fh) and the FSR register is ignored. For direct addressing with bit 4 of “fr” equal to 1 (fr=10-1F), the three high-order bits of the FSR
register specify the bank number accessed, and the five bits of “fr” specify which register in that bank
is accessed. In this case, the upper half of a bank is accessed. 2.3.3 SX48/52BD Addressing Modes and FSR Register Each  SX  instruction  that  accesses  a  data  memory  register  contains  a  5-bit  field  in  the  instruction opcode that specifies the register to be accessed. The abbreviation “fr” (file register) represents the 5-
bit register address designator. For example, the instruction description “mov fr,W” means that a 5-bit
value or label must be substituted for “fr” in the instruction, such as “mov $0F,W” (to move the con-
tents of the working register W into file register 0Fh).
There are three different addressing modes, called the indirect, direct, and semi-direct modes. The
addressing mode used for register access depends on the 5-bit “fr” value used in the instruction:
•   indirect mode: fr = 00h
•   direct mode (fr bit 4 = 0): fr = 01h through 0Fh
•   semi-direct mode (fr bit 4 = 1): fr = 10h through 1Fh Figure 2-2 illustrates the data memory addressing scheme. For indirect addressing (fr=00), the File Select Register (FSR) specifies the register to be accessed.
FSR is an 8-bit, memory-mapped register (at address 04h) which serves as an 8-bit pointer into data