© 2000 Scenix Semiconductor, Inc. All rights reserved. 23 SX User’s Manual Rev. 3.1 www.scenix.com Chapter 2 Architecture The  organization  of  the  data  memory  banks  is  somewhat  different  for  the  various  SX  family  8
members: • SX18/SX20/SX28AC and SX18/20/28AC75: eight banks of 16 bytes per bank, with 8 global
registers mapped to bank 0 • SX48BD/SX52BD: 16 banks of sixteen bytes per bank, with 16 global registers mapped into a
separate bank The following sections describe the bank organization in detail. 2.3.2 SX18/20/28AC and SX18/20/28AC75 Addressing Modes and FSR Register The data memory of the SX18AC, SX20AC, SX28AC, SX18AC75, SX20AC75, or SX28AC75 is a
RAM-based  register  set  consisting  of  136  general-purpose  registers  and  eight  dedicated-purpose
registers.  All  of  these  registers  are  eight  bits  wide.  The  registers  are  organized  into  eight  banks,
designated Bank 0 through Bank 7. Each  SX  instruction  that  accesses  a  data  memory  register  contains  a  5-bit  field  in  the  instruction opcode that specifies the register to be accessed. The abbreviation “fr” represents the 5-bit register
address designator. For example, the instruction description “mov fr,W” means that a 5-bit value or
label must be substituted for “fr” in the instruction, such as “mov $0F,W” (to move the contents of the
working register W into file register 0Fh). The SX device can be programmed to use any one of the eight banks at any given time. The three high-
order bits in the File Select Register (FSR) specify the current bank number. To change from one bank
to  another,  the  program  can  either  write  an  eight-bit  value  to  the  FSR  register  or  use  the  “bank”
instruction. The “bank” instruction writes the three bank-selection bits in the FSR register without
affecting the other bits in the register. Bank 0 is selected by default upon power-up or reset. Within each bank, there are 32 available addresses, ranging from 00h to 1Fh.  Table 2-1 shows the
organization of file registers in the memory-mapped address space. The numbers along the left side the
table (ranging from $00 to $1F) show the 32 possible register addresses that can be specified in the
instruction. The bank numbers listed across the top (ranging from 0 to 7) are the numbers that can be
programmed into the three high-order bits of the FSR register. The entries inside the table show the
registers accessed by each combination of register address and bank selection. The 5-bit register addresses along the left side are shown as they are written in the syntax of the SX
assembly language, using a dollar sign ($) indicating the beginning of a hexadecimal value. Inside the
table, the register addresses are shown as 8-bit hexadecimal values.