© 2000 Scenix Semiconductor, Inc. All rights reserved. 169 SX User’s Manual Rev. 3.1 www.scenix.com Chapter 8 Multi-Function Timers 8.4.1 Timer T1 Control A Register (T1CNTA) T1CPF2 T1CPF1 T1CPIE T1CMF2 T1CMF1 T1CMIE T1OVF T1OVIE 7 6 5 4 3 2 1 0 Table 8-2  T1CNTA Register Bits Bit Name Description T1CPF2 Timer T1 Capture Flag 2. In Capture/Compare mode, this flag is automatically set to 1 when a capture
event occurs on the Capture 2 pin of Timer T1 (pin RB5). It stays set until cleared by the software. T1CPF1 Timer T1 Capture Flag 1. In Capture/Compare mode, this flag is automatically set to 1 when a capture
event occurs on the Capture 1 pin of Timer T1 (pin RB4). It stays set until cleared by the software. T1CPIE Timer T1 Capture Interrupt Enable. Set this bit to 1 to enable capture interrupts for Timer T1 in Cap-
ture/Compare mode. In that case, an interrupt will occur each time a valid edge is received on the Cap-
ture 1 or Capture 2 pin of Timer T1. Clear this bit to 0 to disable capture interrupts. T1CMF2 Timer T1 Comparison Flag 2. This flag is automatically set to 1 when the contents of the timer counter
match the contents of R2, when R2 is the active comparison register. The flag stays set until it is
cleared by the software. T1CMF1 Timer T1 Comparison Flag 1. This flag is automatically set to 1 when the contents of the timer counter
match the contents of R1, when R1 is the active comparison register. The flag stays set until it is
cleared by the software. T1CMIE Timer T1 Comparison Interrupt Enable. Set this bit to 1 to enable comparison interrupts for Timer T1.
In that case, an interrupt will occur each time the contents of the timer counter match the contents of
the active comparison register (R1 or R2) of Timer T1. Clear this bit to 0 to disable comparison inter-
rupts. T1OVF Timer T1 Overflow Flag. This flag is automatically set to 1 when the timer counter overflows from
FFFFh to 0000h. The flag stays set until it is cleared by the software. T1OVIE Timer T1 Overflow Interrupt Enable. Set this bit to 1 to enable overflow interrupts for Timer T1. In
that case, an interrupt will occur each time Timer T1 overflows. Clear this bit to 0 to disable overflow
interrupts.