SX User’s Manual Rev. 3.1 156 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 6 Timers and Interrupts • an interrupt signal received on a Port B input pin that has been configured for Multi-Input Wake-
up/Interrupt operation RTCC interrupts can be used to keep track of elapsed time (for example, to maintain a real-time clock
that changes the displayed time once per second). Port B interrupts can be used to handle any type of
external device that needs service, such as a hardware peripheral or a serial interface. The SX48/52BD
devices have additional interrupt sources associated with the multi-function timers T1 and T2. 6.4.1 Single-Level Interrupt Operation All interrupts are global in nature; that is, no interrupt has priority over another. Interrupts are handled
sequentially. Once an interrupt is acknowledged, all subsequent interrupts are disabled until return
from servicing the current interrupt. The PC is pushed onto the single level interrupt stack, and the
contents of the FSR, STATUS, and W registers are saved in their corresponding shadow registers. Bits  PA0,  PA1, and  PA2,  of  the  STATUS  register  are cleared  after  the  STATUS  register  has been saved in its corresponding shadow register. The interrupt logic has its own single-level stack and is
not part of the CALL subroutine stack. The vector for the interrupt service routines is address 0. Once in the interrupt service routine, the user program must check all interrupt pending bits to deter-
mine the source of the interrupt. The interrupt service routine should clear the corresponding interrupt
pending flag.
Normally it is a requirement for the user program to process every interrupt without missing any. To
ensure this, the longest path through the interrupt routine must take less time than the shortest possi-
ble delay between interrupts. The Multi-Input Wakeup/Interrupt circuit continues to operate during an interrupt service routine. It
senses valid edges on the enabled wakeup/interrupt input pins and sets the WKPND_B pending flags
accordingly.  However,  these  interrupt  events  are  not  serviced  until  the  current  service  routine  is
completed. If more than one interrupt condition occurs during an interrupt service routine, the pending interrupts
can be serviced in any order upon completion of the current interrupt service routine. There is no
“priority” associated with different interrupt sources. 6.4.2 Interrupt Sequence The following sequence takes place in processing an interrupt: 1.   The interrupt condition occurs (either an RTCC rollover or a Multi-Input Wakeup/Interrupt sig- nal on Port B). An interrupt is generated only if the applicable condition is enabled to operate as
an interrupt. 2.   The CPU automatically saves the current contents of the program counter (all 12 bits) and the W, STATUS, and FSR registers. It saves these register contents in a set of independent shadow reg-
isters, not in the program stack. All further interrupts are disabled. 3.   The program jumps to address 000h, where the interrupt service routine should be located. 4.   If the device is configured to accept different interrupts, the interrupt service routine should read the applicable registers (such as WKPND_B and T1CNTB) to determine the cause of the inter-
rupt.