SX User’s Manual Rev. 3.1 154 © 2000 Scenix Semiconductor, Inc. All rights reserved. www.scenix.com Chapter 6 Timers and Interrupts such flag. In that case, the interrupt service routine should read the RTCC register to determine whether
an RTCC rollover caused the interrupt. A register value of 00h (or a very low value) is an indicator that
a rollover has just occurred. 6.3 Watchdog Timer The Watchdog timer is a circuit that provides an automatic escape route from infinite loops and other
abnormal program conditions. It can be enabled or disabled by the WDTE (Watchdog Timer Enable)
bit in the FUSE word register. In the default configuration, the Watchdog timer is enabled. The timer has an 8-bit register that is incremented by an independent on-chip oscillator, completely
separate from the on-chip RC oscillator that can be used to drive the rest of the device. The counter
counts up from 00h to FFh. When the counter rolls over from FFh to 00h (or rolls over the number of
times programmed into the prescaler register), it generates a device reset and clears the TO (Timeout)
flag in the STATUS register to indicate that a Watchdog timeout has occurred. To prevent this automatic reset, the application program must periodically set the timer back to zero.
This is accomplished by executing the “CLR !WDT” (clear Watchdog Timer) instruction, which clears
the  Watchdog  timer  register  and  prescaler  register  to  zero.  Executing  this  instruction  is  called
“servicing” the Watchdog. The Watchdog timer register is not memory-mapped and is not accessible
by any other means. If the program gets stuck in an infinite loop, it is unlikely to service the Watchdog in that loop. In that
case, when the Watchdog counts up to FFh and rolls over to 00h (or rolls over a specified number of
times), the device is reset automatically, thus providing an escape from the infinite loop. A rollover
also clears the TO (Timeout) flag. The “CLR !WDT” instruction, in addition to clearing the Watchdog timer register, also sets the TO
and PD flags to 1 in the STATUS register. The TO flag is cleared to 0 to indicate the occurrence of a
Watchdog timeout. The PD flag is cleared to 0 by the “SLEEP” instruction to indicate that the device
has been put into the power down mode. 6.3.1 Watchdog Timeout Period The  Watchdog  oscillator  has  a  nominal  operating  frequency  of  14  kHz,  or  a  period  of  714
microseconds. At this rate, the 8-bit counter counts from 00h to FFh in 18 milliseconds. This amount
of time is the default Watchdog timeout period. The application program needs to execute a “CLR
!WDT” instruction at least once every 18 milliseconds to prevent a Watchdog reset. The Watchdog timeout period can be increased by using the 8-bit prescaler register. This register can
be configured to operate with either the Watchdog timer or RTCC circuit, but not both at the same time.
This selection is controlled by the PSA (Prescaler Assignment) bit in the OPTION register. If the prescaler register is used with the Watchdog timer, it actually operates as a postscaler that causes
a device reset to occur after the 8-bit Watchdog register overflows a certain number of times. This
increases the Watchdog timeout period by a factor determined by the PS2:PS0 bits in the OPTION