© 2000 Scenix Semiconductor, Inc. All rights reserved. 153 SX User’s Manual Rev. 3.1 www.scenix.com Chapter 6 Timers and Interrupts 6.2.3 RTCC Operation as a Real-Time Clock or Timer To use the RTCC circuit as a real-time clock, configure it to be incremented by the instruction clock.
In that case, the RTCC counter is incremented at a fixed rate of once per instruction clock cycle. For
example, if the instruction rate is 4 MHz, The RTCC counter is incremented at 4 MHz, or once per 250
nsec. The accuracy of the timer depends only on the accuracy of the clock that drives the SX device. To increment the RTCC counter at slower rate, enable the prescaler register and specify the divide-by
factor using the PS2:PS0 bits in the OPTION register. To operate the RTCC as a count-down timer, initialize the RTCC register to the appropriate value and
let  the  counter  run.  For  example,  to  count  100  instruction  cycles,  load  RTCC  with  the  value  156
(decimal) using an instruction such as “mov $01,#156”. The RTCC counter will then increment the
register 100 times before it reaches the maximum value and rolls over back to zero,  triggering an
interrupt (if enabled by the RTE_IE bit in the OPTION register). If you power down the device using the “SLEEP” instruction, the device clock is stopped, the RTCC
counter stops operating, and the RTCC register contents are lost. Upon wakeup from the power down
mode, the RTCC register contains unknown data. On the SX18/20/28 devices, there is no interrupt pending bit to indicate the overflow occurence.The
RTCC register must be sampled by the program to determine any overflow occurrence. 6.2.4 RTCC Operation as an Event Counter To use the RTCC circuit as an external event counter, configure it to be incremented by pulses on the
RTCC input pin. Design the system to generate a pulse for each occurrence of the event, and feed that
signal into the RTCC pin. Then the RTCC counter is incremented once for each occurrence of the
external event. Use the RTE_ES bit in the OPTION register to specify the type of transition to be
sensed on the RTCC pin (rising or falling edges). To increment the RTCC counter at slower rate, enable the prescaler register and specify the divide-by
factor using the PS2:PS0 bits in the OPTION register. The RTCC circuit can count no more than one event per instruction cycle. Multiple edges received
within a single instruction cycle are counted as a single event. 6.2.5 RTCC Overflow Interrupts The device can be configured to generate an interrupt each time the RTCC register rolls over from FFh
to 00h. To do this requires the following actions: • Clear the OPTION_X bit in the FUSE word register when you program the device. This enables
operation of the RTW and RTE_IE bits in the OPTION register. • Have the software clear the RTE_IE bit in the OPTION register. The  SX48/52BC  has  an  interrupt  pending  flag  associated  with  RTCC  rollover  interrupts,  called
RTCCOV (RTCC Overflow), which is bit 7 in the T1CNTB register. The interrupt service routine can
check this bit to determine whether an RTCC overflow caused the interrupt. The SX18/20/28 has no