The data memory of the SX18AC, SX20AC, SX28AC, SX18AC75, SX20AC75, or SX28AC75 is a RAM-based register set consisting of 136 general-purpose registers and eight dedicated-purpose registers. All of these registers are eight bits wide. The registers are organized into eight banks, designated Bank 0 through Bank 7.
Each SX instruction that accesses a data memory register contains a 5-bit field in the instruction opcode that specifies the register to be accessed. The abbreviation “fr” represents the 5-bit register address designator. For example, the instruction description “mov fr,W” means that a 5-bit value or label must be substituted for “fr” in the instruction, such as “mov $0F,W” (to move the contents of the working register W into file register 0Fh).
The SX device can be programmed to use any one of the eight banks at any given time. The three high-order bits in the File Select Register (FSR) specify the current bank number. To change from one bank to another, the program can either write an eight-bit value to the FSR register or use the “bank” instruction. The “bank” instruction writes the three bank-selection bits in the FSR register without affecting the other bits in the register. Bank 0 is selected by default upon power-up or reset.
Within each bank, there are 32 available addresses, ranging from 00h to 1Fh. Table 2-1 shows the organization of file registers in the memory-mapped address space. The numbers along the left side the table (ranging from $00 to $1F) show the 32 possible register addresses that can be specified in the instruction. The bank numbers listed across the top (ranging from 0 to 7) are the numbers that can be programmed into the three high-order bits of the FSR register. The entries inside the table show the registers accessed by each combination of register address and bank selection.
The 5-bit register addresses along the left side are shown as they are written in the syntax of the SX assembly language, using a dollar sign ($) indicating the beginning of a hexadecimal value. Inside the table, the register addresses are shown as 8-bit hexadecimal values.
For the first 16 addresses that can be specified in an instruction (00h through 0Fh), the same 16 registers are accessed, irrespective of the bank setting. Therefore, these 16 “global” registers are always accessible. The first eight are dedicated-purpose registers (INDF, RTCC, PC, and so on), and the next eight are general-purpose registers. In Table 2-1, these registers are shown shaded in Bank 1 through Bank 7 to indicate that they are the same registers as in Bank 0.
For the upper 16 addresses that can be specified in an instruction (10h through 1Fh), a different set of registers is accessed in each bank. This allows as many as 128 different registers to be accessed in this memory range, although only 16 are accessible at any given time.
The total number of general-purpose registers is 24 in Bank 0 (from 08h to 1Fh) and 16 in each of the remaining seven banks (from 10h to 1Fh in each bank), for a total of 136 registers. In the SX18AC/SX18AC75 and SX20AC/SX20AC75 devices, an additional general-purpose register is available at address 08h because there is no Port C register occupying that address.
There are two addressing modes for the SX18/20/28AC and SX18/20/28AC75 devices, called the indirect and direct modes. The addressing mode used for register access depends on the 5-bit “fr” value used in the instruction:
• indirect mode: fr = 00h
• direct mode: fr = 01h through 1Fh
For indirect addressing (fr=00), the File Select Register (FSR) specifies the register to be accessed. FSR is an 8-bit, memory-mapped register (at address 04h) which serves as an 8-bit pointer into data memory for indirect addressing.
For direct addressing with bit 4 of “fr” equal to 0 (fr=01-0F), Bank 0 is accessed and the value of “fr” itself specifies the register to be accessed. In this case, a “global” register in Bank 0 is accessed (01h through 0Fh) and the FSR register is ignored.
For direct addressing with bit 4 of “fr” equal to 1 (fr=10-1F), the three high-order bits of the FSR register specify the bank number accessed, and the five bits of “fr” specify which register in that bank is accessed. In this case, the upper half of a bank is accessed.
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