acknowledge (ACK) signal is received, before sending the address byte and then writing or reading the data byte.
This is done because the EEPROM enters into an internal write cycle after each write operation, and cannot be
accessed until the preceeding write process is complete, which for the 24LC01 is on the order of 10 msec. Thus
by using acknowledge polling, subsequent write or read operations are executed as soon as possible after a
preceeding write.                 To read from the 24LC01 in random access mode, the procedure is essentially identical to the write
process except that after the initial control byte and address byte have been sent and an ACK received, a new
START signal is then sent followed by a read control byte (10100001b). The SDA line is then switched to an
input, and data is clocked in from the EEPROM instead of sent out. The procedure is signaled as complete, as
during a write, by generating a final STOP signal.                 A START signal is generated by toggling the SDA line from high to low (creating a falling edge) while
the SCL line is held high. A STOP signal is generated in the same manner except that SDA is toggled from low
to high, thus creating a rising edge. An ACK signal is received after 8 control, address or data bits have been
sent, and is considered valid if the SDA line is held low during the following (i.e. the 9th) SCL toggle cycle.                 During all operations, the timing between changes in the SCL and SDA lines is a crucial factor. In this
case, a generic delay time has been selected for all required START, STOP, data I/O, and ACK delays.  As
given, the program is capable of reading the EEPROM at approximately 200kbps⁴ with the SX in turbo mode.                 When calling the I2C_write and I2C_read subroutines, the program register bank must be set to the I2C
bank. For random access mode, the address of the byte to be written/read must be pre-loaded into the address⁵
program register, and the sequential flag seq_flag must be set to low. For writes, the byte to be written must be
also be pre-loaded into the data program register, and for reads, the data program register will contain the value
received from the EEPROM upon completion of the read procedure. Modifications and further options To optimize access speed to the 24LC01, the specific event and signal timings should be taken from the 24LC01 data sheet, and the appropriate reduced delay values inserted into the various bit operation subroutines.
The Bus_delay subroutine can be accessed to produce a customized delay by loading the W register with the
delay value and then calling Bus_delay:custom. In turbo mode each custom call will cause the following timing
delay:   delay [usec] = 1/xtal[MHz] * (6 + 4 * (W-1)), where xtal is the oscillator frequency in MHz and W is the
value pre-loaded into the W register. For example, a value in W=62 will cause a 5 usec delay at 50 MHz.                 Performing sequential writes and reads will also speed up the rate at which the 24LC01 can be accessed,
and especially significantly increase the rate at which the 24LC01 can be written (since up to 8 bytes can be
written simultaneously, reducing the need for separate internal EEPROM write delays).                 To perform a sequential write, a specific series of steps must be followed. First the sequential flag
seq_flag must be set high. The first byte to be written is then written as usual, but the following bytes (up to 7
more) are written by calling the write routine at the I2C_write:sequential entry point. Take note that seq_flag
must be reset to low before the final byte of the group is sent, though the entry point called to write this final
byte is still I2C_write:sequential. This generates the required stop bit to initiate the EEPROM internal write
sequence.                 To perform a sequential read, a similar series of steps must be followed. First the sequential flag
seq_flag must be set high. The first byte to be read is read as usual, but the following bytes (up to the length of                                                        ⁴Since this implementation of the I2C access is coupled with a with a program that uses the SX's internal RTCC interrupt, the actual
timing of the EEPROM access will vary per read/write, depending on how often interrupts occur during the read/write sequence.
⁵Take care to set the appropriate register bank, if needed.