© 2000 Scenix Semiconductor, Inc. All rights reserved. 5 SX Device Programming Specifications Rev 2.2 www.scenix.com 2.2.1 External Clocking When the device is clocked by external components or an external clock signal, the programmer unit
should use the following procedure to place the SX device in the ISP programming mode: 1.   Drive the OSC1 pin low to stop the clock. 2.   Drive the OSC2 pin low and toggle the OSC1 pin at least nine times. This is the signal to enter the ISP mode. OSC2 pin will be configured as open drain. 3.   Release the OSC2 pin. OSC2 pin will be pull high by SX. 4.   Apply the VPP programming voltage to the OSC1 pin. The SX internal RC oscillator starts op- erating at 128 kHz. This clock drives the SX device during ISP mode programming. 2.2.2 Internal RC Oscillator When the device is clocked by the internal RC oscillator, the programmer unit should use the following
procedure to place the SX device in the ISP programming mode: 1.   Drive the OSC2 pin low for at least nine internal clock cycles. The internal clock frequency can be any one of eight values ranging from 32 kHz to 4 MHz, depending on the divide-by rate pro-
grammed into the FUSE word. 2.   Release the OSC2 pin. 3.   Apply the VPP programming voltage to the OSC1 pin. The SX internal RC oscillator starts op- erating at 128 kHz. This clock drives the SX device during ISP mode programming. 2.3 Programming in ISP Mode Upon entry into the ISP mode, the SX device could be in the middle of executing a program, possibly
with some I/O ports configured as outputs and driving other devices in the system. The first action of
the ISP logic is to reset the SX device. This puts the device into a known logic state and configures the
I/O ports to operate as inputs, thus preventing possible damage to other components in the system. After  the  device  is  reset,  the  ISP  logic  executes  the  ISP  protocol.  This  is  a  “self-aligned”  serial
communication  protocol  that  uses  the  OSC2  pin  for  both  synchronization  and  for  serial  I/O.  No
separate clock pin is needed in this protocol. The OSC2 pin is implemented with an open drain and an
internal pullup, allowing it to operate as an input or output. 2.3.1 Frames, Cycles, and Internal Clocks Communication is carried out in packets called “frames.” Each frame consists of 17 cycles, and each
cycle consists of four internal clocks. The period of the internal clock is 7.81 microseconds (frequency
is 128 KHz), so each cycle is 31.3 microseconds and each frame is 531 microseconds. Figure 2.3 shows the timing of an ISP frame. The frame consists of 17 cycles. The first cycle is the
“sync” cycle, used to synchronize the programmer unit to the ISP frame. This is followed by four
“command” cycles, designated C3 through C0. The programmer unit drives the OSC2 pin during these