© 2000 Scenix Semiconductor, Inc. All rights reserved. - 8 - www.scenix.com SX48BD/SX52BD/SX52BD75/SX52BD100 3.0 PORT DESCRIPTIONS The device contains five 8-bit I/O ports (Port A through Port E). Port A provides symmetrical drive capability. In the 48-pin version of the device, Port A has only four pins rather  than  eight.  The  unavailable  pins  are  pulled  high. Each  port  has  four  associated  8-bit  registers  (Direction, Data, TTL/CMOS Select, and Pull-Up Enable) to config- ure each port pin as Hi-Z input or output, to select TTL or CMOS  voltage  levels,  and  to  enable/disable  the  weak pull-up  resistor.  The  least  significant  bit  of  the  registers corresponds  to  the  least  significant  port  pin.  To  access these configuration registers, an appropriate value must be written into the MODE register. Upon power-up, all bits in these registers are initialized to “1”. The associated registers allow for each port bit to be indi- vidually   configured   under   software   control   as   shown below: Ports B, C, D, and E have additional associated registers (Schmitt-Trigger  Enable  Registers  ST_B  and  ST_C)  to enable  or  disable  the  Schmitt  Trigger  function  on  each individual port pin as indicated in table below. Port B also supports the on-chip differential comparator. Ports  RB1  and  RB2  are  the  comparator  negative  and positive inputs, respectively, while Port RB0 is the com- parator  output  pin.  Port  B  also  supports  the  Multi-Input Wakeup feature on all eight pins. Port B and Port C also support the multi-function timers T1 and T2. RB4 and RB5 are the T1 capture inputs, RB6 is the T1 PWM output, and RB7 is the T1 external event counter input. Similarly, RC0 and RC1 are the T2 capture inputs,  RC2  is  the  T2  PWM  output,  and  RC3  is  the  T2 external event counter input. Figure3-1  shows  the  internal  hardware  structure  and configuration registers for each pin of Port A. Figure3-2 shows the same for each pin of Port B, C, D, or E. 3.1 Reading and Writing the Ports The five ports are memory-mapped into the data memory address space. To the CPU, the five ports are available as  the  RA,  RB,  RC,  RD,  and  RE  file  registers  at  data memory  addresses  05h  through  09h,  respectively.  Writ- ing  to  a  port  data  register  sets  the  voltage  levels  of  the corresponding  port  pins  that  have  been  configured  to operate as outputs. Reading from a data register reads either the voltage levels of the corresponding port pins or the data contained in the port data register depending on the status PORTRD bit contained in the T2CNTB regis- ter. Table 3-1.  Port Configuration Data Direction Registers: RA, RB, RC, RD, RE TTL/CMOS Select Registers: LVL_A, LVL_B, LVL_C, LVL_D, LVL_E Pullup Enable Registers: PLP_A, PLP_B, PLP_C, PLP_D, PLP_E 0 1 0 1 0 1 Output Hi-Z Input CMOS TTL Enable    Disable Table 3-2.  Schmitt Trigger Select Schmitt Trigger Enable Registers: ST_B, ST_C, ST_D, ST_E 0 1 Enable Disable