© 2000 Scenix Semiconductor, Inc. All rights reserved.
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SX48BD/SX52BD/SX52BD75/SX52BD100
17.4
DC Characteristics
SX52BD75/SX52BD100: Operating Temperature 0°C <= Ta <= +70°C (Commercial)
Note 1: Bit 4 of the FUSE register must is reset to 0.
Note 2: Vdd must start rising from Vss to ensure proper Power-On-Reset when relying on the internal Power-On-Reset
Circuitry.
Note 3: External clock, with bit 4 of the FUSE register reset to 0. No floating inputs.
Note 4: The FUSE register contains 0AAh.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Vdd
Supply Voltage
(Note 1)
Fosc = 0 - 75MHz
Fosc = 0 - 100MHz
4.5
4.75
–
5.5
5.25
V
V
SVdd
Vdd rise rate to ensure Power-
On Reset (Note 2)
–
0.05
–
-
V/ms
Idd
Supply Current, active
(Note 3)
Vdd = 5.0V, Fosc = 75 MHz
Vdd = 5.0V, Fosc = 100 MHz
-
106
140
150
190
mA
mA
Ipd
Supply Current, power down
Vdd = 5.0V, WDT disabled and
SLEEPCLK disabled
Vdd = 5.0V, WDT enabled and
SLEEPCLK disabled
-
1
50
300
400
µA
µA
Vih, Vil
Input Levels
MCLR, RTCC
Logic High
Logic Low
OSC1
Logic High
Logic Low
All Other Inputs
CMOS
Logic High
Logic Low
TTL
Logic High
Logic Low
0.9Vdd
Vss
0.7Vdd
Vss
0.7Vdd
Vss
2.0
Vss
Vdd
0.1Vdd
Vdd
0.3Vdd
Vdd
0.3Vdd
Vdd
0.8
V
V
V
V
V
V
V
V
V
V
Iil
Input Leakage Current
Vin = Vdd or Vss (Note 4)
-3.0
+3.0
µA
Ipup
Weak Pullup Current
Vdd = 5.5V, Vin = 0V
250
430
600
µA
Voh
Output High Voltage
Ports B, C, D, E
Port A
Ioh = 14mA, Vdd = 4.5V
Ioh = 25mA, Vdd = 4.5V
Vdd-0.7
Vdd-0.7
V
V
Vol
Output Low Voltage
All Ports
Iol = 25mA, Vdd = 4.5V
0.6
V
