© 2000 Scenix Semiconductor, Inc. All rights reserved. - 45 - www.scenix.com SX48BD/SX52BD/SX52BD75/SX52BD100 15.12    Comparison and Conditional Branch Instructions The instruction set includes instructions such as DECSZ fr  (decrement  file  register  and  skip  if  zero),  INCSZ  fr (increment file register and skip if zero), SNB bit (bit test file register and skip if bit clear), and SB bit (bit test file register and skip if bit set). These instructions will cause the next instruction to be skipped if the tested condition is true.  If  a  skip  instruction  is  immediately  followed  by  a PAGE  or  BANK  instruction  (and  the  tested  condition  is true) then two instructions are skipped and the operation consumes  three  cycles.  This  is  useful  for  conditional branching  to  another  page  where  a  PAGE  instruction precedes a JMP. If several PAGE and BANK instructions immediately  follow  a  skip  instruction  then  they  are  all skipped plus the next instruction and a cycle is consumed for each. 15.13    Logical Instruction The instruction set contain a full complement of the logi- cal  instructions  (AND,  OR,  Exclusive  OR),  with  the  W register  and  a  selected  memory  location  (using  either direct  or  indirect  addressing)  serving  as  the  two  oper- ands. 15.14    Shift and Rotate Instructions The  instruction  set  includes  instructions  for  left  or  right rotate-through-carry. 15.15    Complement and SWAP The device can perform one’s complement operation on the  file  register  (fr)  and  W  register.  The  MOV  W,<>fr instruction  performs  nibble-swap  on  the  fr  and  puts  the value into the W register. 15.16    Key to Abbreviations and Symbols Symbol Description W Working register fr File register (memory-mapped register in the range of 00h to FFh) PC Lower eight bits of program counter (file regis- ter 02h) STATUS   STATUS register (file register 03h) FSR File Select Register (file register 04h) C Carry bit in STATUS register (bit 0) DC Digit Carry bit in STATUS register (bit 1) Z Zero bit in STATUS register (bit 2 PD Power Down bit in STATUS register (bit 3) TO Watchdog Timeout bit in STATUS register (bit 4) PA2:PA0  Page select bits in STATUS register (bits 7:5) OPTION   OPTION register (not memory-mapped) WDT Watchdog Timer register (not memory- mapped) MODE MODE register (not memory-mapped) rx Port control register pointer (RA, RB, RC, RD, RE) ! Non-memory-mapped register designator f File register address bit in opcode k Constant value bit in opcode n Numerical value bit in opcode b Bit position selector bit in opcode . File register / bit selector separator in assem- bly language instruction # Immediate literal designator in assembly lan- guage instruction lit Literal value in assembly language instruction addr8 8-bit address in assembly language instruction addr9 9-bit address in assembly language instruction addr12 12-bit address in assembly language instruc- tion / Logical 1’s complement | Logical OR ^ Logical exclusive OR & Logical AND <> Swap high and low nibbles (4-bit segments) << Rotate left through carry flag >> Rotate right through carry flag - - Decrement file register ++ Increment file register