© 2000 Scenix Semiconductor, Inc. All rights reserved. - 42 - www.scenix.com SX48BD/SX52BD/SX52BD75/SX52BD100 15.3 Addressing Modes The device support the following addressing modes: Data Direct Data Indirect Data Semidirect Immediate Program Direct Program Indirect Relative Both direct and indirect addressing modes are available. The INDF register, though physically not implemented, is used in conjunction with the indirect data pointer (FSR) to perform indirect addressing. An instruction using INDF as its  operand  field  actually  performs  the  operation  on  the register  pointed  by  the  contents  of  the  FSR.  Conse- quently, processing two multiple-byte operands requires alternate loading of the operand addresses into the FSR pointer as the multiple byte data fields are processed. Examples: Direct addressing: Indirect Addressing: Semidirect Addressing: 15.4 The Bank Instruction Often it is desirable to set the bank select bits of the FSR register  in  one  instruction  cycle.  The  Bank  instruction provides this capability. This instruction sets the upper  3 bits 4, 5 and 6 of the FSR to point to a specific RAM bank without affecting the lower 4 FSR bits, in preparation for using direct  or  semidirect  addressing.  Bit  7  of  the  FSR register  is  used  to  select  the  lower  or  upper  block  of banks. Example: 15.5 Bit Manipulation The instruction set contains instructions to set, reset, and test individual bits in data memory. The device is capable of bit addressing anywhere in data memory. 15.6 Input/Output Operation The device contains three registers associated with each I/O port. The first register (Data Direction Register), con- figures each port pin as a Hi-Z input or output. The sec- ond  register  (TTL/CMOS  Register),  selects  the  desired input level for the input. The third register (Pull-Up Regis- ter), enables a weak pull-up resistor on the pin configured as a input. To read or write these registers, you must first write  an  appropriate  value  into  the  MODE  register  to select  the  desired  register  set,  and  then  use  the  “mov !rx,W” instruction to read or write the register.    15.6.1  Read-Modify-Write Considerations When two successive instructions are used on the same I/O port (except “mov Rx, W”) with a very high clock rate, the  “write”  part  of  one  instruction  might  not  occur  soon enough before the “read” part of the very next instruction, resulting in getting “old” data for the second instruction. To  ensure  predictable  results,  avoid  using  two  succes- sive read-modify-write instructions that access the same port data register if the clock rate is high or, insert 3 NOP instructions   between   the   successive   read-modify-write instructions (if SYNC bit in the FUSE register is enabled, 5 NOP instructions are required). For operating frequen- cies  of  50  Mhz  or  lower,  if  bit  7  of  the  T2CNTB  (POR- TRD)  is  set,  the  port  reads  data  from  the  data  register instead  of  port  pins.  In  this  case,  the  NOP  instructions are not required. In the default device configuration, when a read is per- formed from a port bit position, the operation is actually reading the voltage level on the pin itself, not necessarily the bit value stored in the port data register. This is true whether the pin is configured to operate as an input or an output. Therefore, with the pin configured to operate as an input, the data register contents have no effect on the value that you read. With the pin configured to operate as an output, what is read generally matches what has been written to the register. PORTRD of the T2CNTB register determines how the device reads data from its I/O ports (Port  A  through  Port  E).  Clear this  bit  to  0  to  have  the device read data from the port I/O pins directly. Set this bit to 1  to have the device read data from the port data registers. Under normal output mode conditions, it should not matter which method you use to read the port data. However, if a port pin is configured as an output and an external circuit forces the pin to the opposite value, the value read from the port will depend on the reading mode used. Note that this control bit is not related to multi-func- tion timers T1 and T2. 15.7 Increment/Decrement The current selected bank of 31 registers serves as a set of accumulators. The instruction set contains instructions to increment and decrement the register file. The device also  includes  both  INCSZ  fr  (increment  file  register  and skip  if  zero)  and  DECSZ  fr  (decrement  file  register  and skip if zero) instructions. 15.8 Loop Counting and Data Pointing Testing The   device   has   specific   instructions   to   facilitate   loop counting. The DECSZ fr (decrement file register and skip if  zero)  tests  any  one  of  the  file  registers  and  skips  the next instruction (which can be a branch back to loop) if the result is zero. mov W,#1 mov RA,W ;move “1” to RA mov W,#RA mov FSR,W ;FSR = address of RA mov INDF,#$01 ;move “1” to RA mov W,#$00 mov FSR,W ;FSR = bank 0 address inc $1F ;increment file ;register 0Fh bank    $E0 ;Select Bank E in FSR inc $1F ;increment file register ;EFh using semidirect addressing