© 2000 Scenix Semiconductor, Inc. All rights reserved. - 40 - www.scenix.com SX48BD/SX52BD/SX52BD75/SX52BD100 14.0 REGISTER STATES UPON DIFFERENT RESET CONDITIONS The  effect  of  different  reset  operations  on  a  register depends on the register and the type of reset operation. Some  registers  are  initialized  to  specific  values,  some are left unchanged, some are undefined, and some are initialized to an unknown value. A  register  that  starts  with  an  unknown  value  should  be initialized by the software to a known value; you cannot simply test the initial state and rely on it starting in that state  consistently.  Table14-1  lists  the  SX  registers  and shows the state of each register upon reset, with a differ- ent column for each type of reset. Table 14-1.  Register States Upon Different Resets Register Power-On Wakeup Brown-out Watchdog Timeout MCLR W Undefined Unchanged Undefined Unchanged Unchanged OPTION FFh FFh FFh FFh FFh MODE (Note 3) 1Fh 1Fh 1Fh 1Fh 1Fh RTCC (01h) Undefined Unchanged Undefined Unchanged Unchanged PC (02h) FFh FFh FFh FFh FFh STATUS (03h) (Note 3) Bits 0-2: Unde- fined Bits 3-4: 11 Bits 5-7: 000 Bits 0-2: Un- changed Bits 3-4: Unch. Bits 5-7: 000 Bits 0-4: Unde- fined Bits 5-7: 000 Bits 0-2: Un- changed Bits 3-4: (Note 1) Bits 5-7: 000 Bits 0-2: Un- changed Bits 3-4: (Note 2) Bits 5-7:000 FSR (04h) Undefined Bits 0-6: Un- changed Bit 7: 1 Bits 0-6: Unde- fined Bit 7: 1 Bits 0-6: Un- changed Bit 7: 1 Bits 0-6: Un- changed Bit 7: 1 RA through RE Direction FFh FFh FFh FFh FFh RA through RE Data Undefined Unchanged Undefined Unchanged Unchanged Other File Registers - SRAM Undefined Unchanged Undefined Unchanged Unchanged CMP_B Bits 0, 6-7: 1 Bits 1-5: Unde- fined Bits 0, 6-7: 1 Bits 1-5: Undefined Bits 0, 6-7: 1 Bits 1-5: Unde- fined Bits 0, 6-7: 1 Bits 1-5: Undefined Bits 0, 6-7: 1 Bits 1-5: Undefined WKPND_B Undefined Unchanged Undefined Unchanged Unchanged WKED_B FFh FFh FFh FFh FFh WKEN_B FFh FFh FFh FFh FFh ST_B through ST_E FFh FFh FFh FFh FFh LVL_A through LVL_E FFh FFh FFh FFh FFh PLP_A through PLP_E FFh FFh FFh FFh FFh Watchdog Counter Undefined Unchanged Undefined Unchanged Unchanged Timers T1 and T2 Free- Running Timer/Counter 0001 0001 0001 0001 0001 Timers T1 and T2 Com- pare/Capture Registers 0000 0000 0000 0000 0000 Timers T1 and T2 Control Registers (Note 3) 00 00 00 00 00 NOTE: 1. Watchdog reset during power down mode: 00 (bits TO, PD) Watchdog reset during Active mode: 01 (bits TO, PD) NOTE: 2. External reset during power down mode: 10 (bits TO, PD) External reset during Active mode: Unchanged (bits TO, PD) Note:. 3. MODE, STATUS, and Timer registers are not initialized properly by the development system in Debug mode.