© 2000 Scenix Semiconductor, Inc. All rights reserved. - 39 - www.scenix.com SX48BD/SX52BD/SX52BD75/SX52BD100 A 2-bit field in the FUSEX register can be used to specify the Delay Reset Timer (DRT) timeout period that results in an automatic wake-up from the power down mode. 10 = 0.25 msec 11 = 18 msec (default) 00 = 60 msec 01 = 1 sec For fast start-up from the power down mode, clear the SLEEPCLK bit and set the WDRT1:WDRT0 field to 00. This will keep the clock operating during the power down mode and allow a minimum start-up delay. Note  1:  The external Power-On Reset circuit is required only if V_dd power-up is too slow. The diode D helps dis- charge the capacitor quickly when V_dd powers down and comes back within a short period of time. Note  2:  R  <  40  kW  is  recommended  to  make  sure  that voltage drop across R does not violate the device electri- cal specifications. R1 = 100W to 1kW will limit any current flowing into MCLR from external capacitor C. This helps prevent MCLR pin breakdown due to Electrostatic Discharge (ESD) or Elec- trical Overstress (EOS). 13.0 BROWN-OUT DETECTOR The   on-chip   brown-out   detection   circuitry   resets   the device when V_dd dips below the specified brown-out volt- age.  The  device  is  held  in  reset  as  long  as  V_dd  stays below the brown-out voltage. The device will come out of reset  when  V_dd  rises  above  the  brown-out  voltage.  The brown-out level can be set to 2.2V, 2.4V, OR 4.1V levels through BOR1:BOR0 bits in the FUSEX register.