© 2000 Scenix Semiconductor, Inc. All rights reserved. - 35 - www.scenix.com SX48BD/SX52BD/SX52BD75/SX52BD100 Timer T2 Control B Register (T2CNTB) PORTRD T2CPEDG T2EXEDG T2PS2-T2PS0 T2MC1-T2MC0 7 6 5 4 3 2 1 0 PORTRD Port Read mode. This bit determines how the device reads data from its I/O ports (Port A through Port E). Clear this bit to 0 to have the device read data from the port I/O pins directly. Set this bit to 1 to have the device read data from the port data registers. Under normal (output mode) conditions, it should not matter which method you use to read the port data. However, if a port pin is configured as an output and an external circuit forces the pin to the wrong value, the value read from the port will depend on the reading mode used. Note that this control bit is not related to multi-function timers T1 and T2. T2CPEDG Timer T2 Capture Edge. This bit sets the edge sensitivity of the Timer T2 input capture pins, Capture 1 and Capture 2 (RC0 and RC1). Set this bit to 1 to sense positive-going (low-to-high) edges. Clear this bit to 0 to sense negative-going (high-to-low) edges. T2EXEDG Timer T2 External Event Clock Edge. This bit sets the edge sensitivity of the Timer T2 input used to count external events (RC3). Set this bit to 1 to sense positive-going (low-to-high) edges. Clear this bit to 0 to sense negative-going (high-to-low) edges. T2PS2- T2PS0 Timer T2 Prescaler Divider field. This 3-bit field specifies the divide-by factor for generating the timer clock from the on-chip system clock: 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 For example, setting this field to 010 sets the divide-by factor to 4, which means that the T2 counter register is incremented once every four system clock cycles. T2MC1- T2MC0 Timer T2 Mode Control field. This 2-bit field specifies the Timer T1 operating mode as follows: 00 = Software Timer mode 01 = PWM mode 10 = Capture/Compare mode 11 = External Event mode