© 2000 Scenix Semiconductor, Inc. All rights reserved. - 34 - www.scenix.com SX48BD/SX52BD/SX52BD75/SX52BD100 Timer T2 Control A Register (T2CNTA) T2CPF2 T2CPF1 T2CPIE T2CMF2 T2CMF1 T2CMIE T2OVF T2OVIE 7 6 5 4 3 2 1 0 T2CPF2 Timer T2 Capture Flag 2. In Capture/Compare mode, this flag is automatically set to 1 when a capture event occurs on the Capture 2 pin of Timer T2 (pin RC1). It stays set until cleared by the software. T2CPF1 Timer T2 Capture Flag 1. In Capture/Compare mode, this flag is automatically set to 1 when a capture event occurs on the Capture 1 pin of Timer T2 (pin RC1). It stays set until cleared by the software. T2CPIE Timer T2 Capture Interrupt Enable. Set this bit to 1 to enable capture interrupts for Timer T2 in Cap- ture/Compare mode. In that case, an interrupt will occur each time a valid edge is received on the Cap- ture 1 or Capture 2 pin of Timer T2. Clear this bit to 0 to disable capture interrupts. T2CMF2 Timer T2 Comparison Flag 2. This flag is automatically set to 1 when the contents of the timer counter match  the  contents  of  R2,  when  R2  is  the  active  comparison  register.  The  flag  stays  set  until  it  is cleared by the software. T2CMF1 Timer T2 Comparison Flag 1. This flag is automatically set to 1 when the contents of the timer counter match  the  contents  of  R1,  when  R1  is  the  active  comparison  register.  The  flag  stays  set  until  it  is cleared by the software. T2CMIE Timer T2 Comparison Interrupt Enable. Set this bit to 1 to enable comparison interrupts for Timer T2. In that case, an interrupt will occur each time the contents of the timer counter match the contents of the active comparison register (R1 or R2) of Timer T2. Clear this bit to 0 to disable comparison interrupts. T2OVF Timer  T2  Overflow  Flag.  This  flag  is  automatically  set  to  1  when  the  timer  counter  overflows  from FFFFh to 0000h. The flag stays set until it is cleared by the software. T2OVIE Timer T2 Overflow Interrupt Enable. Set this bit to 1 to enable overflow interrupts for Timer T2. In that case, an interrupt will occur each time Timer T2 overflows. Clear this bit to 0 to disable overflow inter- rupts.