© 2000 Scenix Semiconductor, Inc. All rights reserved. - 33 - www.scenix.com SX48BD/SX52BD/SX52BD75/SX52BD100 Timer T1 Control B Register (T1CNTB) RTCCOV T1CPEDG T1EXEDG T1PS2-T1PS0 T1MC1-T1MC0 7 6 5 4 3 2 1 0 RTCCOV RTCC  Overflow  Flag.  This  flag  is  automatically  set  to  1  when  the  Real-Time  Clock/Counter  (RTCC) overflows from FFh to 00h. This flag stays set until it is cleared by the software. Note that this flag is not related to multi-function timers T1 and T2. T1CPEDG Timer T1 Capture Edge. This bit sets the edge sensitivity of the Timer T1 input capture pins, Capture 1 and Capture 2 (RB4 and RB5). Set this bit to 1 to sense positive-going (low-to-high) edges. Clear this bit to 0 to sense negative-going (high-to-low) edges. T1EXEDG Timer T1 External Event Clock Edge. This bit sets the edge sensitivity of the Timer T1 input used to count external events (RB7). Set this bit to 1 to sense positive-going (low-to-high) edges. Clear this bit to 0 to sense negative-going (high-to-low) edges. T1PS2- T1PS0 Timer T1 Prescaler Divider field. This 3-bit field specifies the divide-by factor for generating the timer clock from the on-chip system clock: 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101= divide by 32 110 = divide by 64 111 = divide by 128 For example, setting this field to 010 sets the divide-by factor to 4, which means that the T1 counter register is incremented once every four system clock cycles. T1MC1- T1MC0 Timer T1 Mode Control field. This 2-bit field specifies the Timer T1 operating mode as follows: 00 = Software Timer mode 01 = PWM mode 10 = Capture/Compare mode 11 = External Event mode