© 2000 Scenix Semiconductor, Inc. All rights reserved. - 30 - www.scenix.com SX48BD/SX52BD/SX52BD75/SX52BD100 Table 10-1.  Mode Register Settings for T1/T2 Registers 10.2 Timer Operating Modes Each timer can be configured to operate in one of the fol- lowing modes: •    Pulse Width Modulation (PWM) mode •    Software Timer mode •    External Event mode •    Capture/Compare mode 10.2.1  PWM Mode In  the  Pulse  Width  Modulation  (PWM)  mode,  the  timer generates  an  output  signal  having  a  programmable  fre- quency and duty cycle. To use this mode, you load two 16-bit comparison registers, R1 and R2, with the number of timer clock cycles that you want the output signal to be high  and  low.  The  contents  of  R1  define  the  PWM  low time while the contents of R2 define the PWM high time. After the “Clear Timer” command is initiated through the MODE register, the timer starts from zero and counts up until it reaches the value in R1. At that point, it generates an  interrupt  (if  enabled),  toggles  the  output  signal  to  a logic high level, and starts counting from zero again. The second time, it counts up until it reaches the value in R2. At that point, it again generates an interrupt (if enabled), toggles the output signal to a logic low level, and starts counting from zero again. This process is repeated con- tinuously,  alternating  between  R1  and  R2  to  obtain  the value at which to toggle the output signal and return the counter to zero. The values of R1 and R2 establish the duty cycle and frequency of the output signal. If R1 and R2 contain the same value, the resulting output signal is a square wave. If R1 is changed to a value less than the timer count while the timer is counting to match R1, the timer will continue to count through FFFFh, and back up to the R1 value, while the output is low. Same is true for R2, except the output signal will be high. Upon reset, the timer/counter is initialized to 0000. In  the  PWM  mode,  the  timer  is  clocked  by  the  on-chip system  clock  divided  by  an  8-bit  prescaler  value.  The divide-by  factor  can  be  set  to  any  power-of-2  from  1  to 256. Thus, the period of the timer clock can be set from 1 to 256 times the system clock period. Upon entering the PWM mode, the internally generated PWM signal is connected to the designated PWM output pin.  The  PWM  mode  bypasses  the  port  data  register (does not affect the contents of the data register). For the PWM  output  signal  to  appear  on  the  pin  (RB6  for  T1, RC2 for T2), the corresponding port pin direction register must be configured for output. 10.2.2  Software Timer Mode The  Software  Timer  mode  is  the  same  as  the  PWM mode,  except  that  the  timer  does  not  toggle  the  output signal.  Instead,  the  application  program  takes  action  in response  to  the  internally  generated  PWM  signal  upon each match between the counter and the contents of the active comparison value in either R1 or R2. The software can  determine  the  cause  of  each  interrupt  by  checking the timer interrupt pending flags. There are different flag bits  associated  with  each  type  of  event  (R1  match,  R2 match, and overflow). 10.2.3  External Event Mode The External Event mode is the same as the PWM mode, except that the counter register is clocked by an external signal provided on an input pin (RB7 for T1 and RC3 for T2) rather than by the system clock. This mode can be used  to  count  the  occurrences  of  external  events.  The input pin can be configured to sense either rising or fall- ing edges. MODE Reg. mov !RB,W mov !RC,W 00h Read T1CPL Read T2CPL 01h Read T1CPH Read T2CPH 02h Read T1R2CML Read T2R2CML 03h Read T1R2CMH Read T2R2CMH 04h Read T1R1CML Read T2R1CML 05h Read T1R1CMH Read T2R1CMH 06h Read T1CNTB Read T2CNTB 07h Read T1CNTA Read T2CNTA 12h Write T1R2CML Write T2R2CML 13h Write T1R2CMH Write T2R2CMH 14h Write T1R1CML Write T2R1CML 15h Write T1R1CMH Write T2R1CMH 16h Write T1CNTB Write T2CNTB 17h Write T1CNTA Write T2CNTA