© 2000 Scenix Semiconductor, Inc. All rights reserved. - 27 - www.scenix.com SX48BD/SX52BD/SX52BD75/SX52BD100 9.0 REAL TIME CLOCK/COUNTER (RTCC)/WATCHDOG TIMER The  device  contains  an  8-bit  Real  Time  Clock/Counter (RTCC)  and  an  8-bit  Watchdog  Timer  (WDT).  An  8-bit programmable prescaler extends the RTCC to 16 bits. If the prescaler is not used for the RTCC, it can serve as a postscaler for the Watchdog Timer. Figure9-1 shows the RTCC and WDT block diagram. 9.1 RTCC RTCC is an 8-bit real-time timer that is incremented once by the internal instruction cycle clock or from a transition on the RTCC pin. The on-board prescaler can be used to extend the RTCC counter to 16 bits. To select the internal clock source, bit 5 of the OPTION register should be cleared. In this mode, RTCC is incre- mented at each instruction cycle unless the prescaler is selected to increment the counter. To select the external clock source, bit 5 of the OPTION register must be set. In this mode, the RTCC pin is sam- pled on each rising edge of the OSC1 pin (the signal fre- quency at the RTTC pin must be less half the frequency on  OSC1).  By  using  bit  4  of  the  OPTION  register,  the transition can be programmed to be either a falling edge or  rising  edge.  Setting  the  control  bit  selects  the  falling edge  to  increment  the  counter.  Clearing  the  bit  selects the rising edge.    The RTCC generates an interrupt (if enabled) as a result of an RTCC rollover from FFh to 00h. Bit 7 of the Timer T1 Control B register is an interrupt pending flag (RTC- COV)  associated  with  this  event.  The  program  should read this flag to determine any rollover occurrence. Writ- ing to the RTCC also clears the prescaler if it is assigned to the RTCC (bit 3 at OPTION register is cleared).Using the  “TEST  fr”  with  RTCC  (with  fr  being  the  RTCC  and RTCC  clock  internally  or  externally)  will  not  allow  the RTCC to increment. The workaround is to use the “MOV W, RTCC” instruction instead. 9.2 Watchdog Timer The watchdog logic consists of a Watchdog Timer which shares the same 8-bit programmable prescaler with the RTCC.  The  prescaler  actually  serves  as  a  postscaler  if used in conjunction with the WDT, in contrast to its use as a prescaler with the RTCC. The WDT is clocked by it’s own internal RC oscillator. The  Watchdog  oscillator  has  a  nominal  operating  fre- quency of 16 kHz, or a period of 62.5 microseconds. At this rate, the 8-bit counter counts from 00h to FFh in 16 milliseconds.    In    the    default    configuration    (prescaler assigned to WDT, with divide rate set to 1:128), the appli- cation program needs to execute a “CLR !WDT” instruc- tion at least once every 2 seconds to prevent a Watchdog reset (if the WDTE bit in the FUSE register is set to 1). 9.3 The Prescaler The 8-bit prescaler may be assigned to either the RTCC or the WDT through the PSA bit (bit 3 of the OPTION reg- ister).  Setting  the  PSA  bit  assigns  the  prescaler  to  the WDT. If assigned to the WDT, the WDT clocks the pres- caler  and  the  prescaler  divide  rate  is  selected  by  the PS0, PS1, and PS2 bits located in the OPTION register. Clearing the PSA bit assigns the prescaler to the RTCC. Once  assigned  to  the  RTCC,  the  prescaler  clocks  the RTCC and the divide rate is selected by the PS0, PS1, and PS2 bits in the OPTION register. The prescaler is not mapped into the data memory, so run-time access is not possible. The prescaler cannot be assigned to both the RTCC and WDT simultaneously.