© 2000 Scenix Semiconductor, Inc. All rights reserved. - 18 - www.scenix.com SX48BD/SX52BD/SX52BD75/SX52BD100 5.0 MEMORY ORGANIZATION 5.1 Program Memory The  program  memory  is  organized  as  4K,  12-bit  wide words.   The   program   memory   words   are   addressed sequentially  by  a  binary  program  counter.  Upon  reset, the program counter is initialized with 0FFFh.  If there is no  branch  operation,  it  will  increment  to  the  maximum value  possible  for  the  device  and  roll  over  and  begin again. Internally,  the  program  memory  has  a  semi-transparent page  structure.  A  page  is  composed  of  512  contiguous program memory words. The lower nine bits of the pro- gram counter are zeros at the first address of a page and ones at the last address of a page. This page structure has  no  effect  on  the  program  counter.  The  program counter  will  freely  increment  through  the  page  bound- aries. 5.1.1  Program Counter The program counter contains the 12-bit address of the instruction to be executed. The lower eight bits of the pro- gram counter are contained in the PC register (02h), and the three upper bits are specified by the STATUS register (PA0,  PA1,  PA2).  Bit  8  is  not  accessible.  Changing the STATUS  bits  is  necessary  to  cause  jumps  and  subrou- tine calls across program memory page boundaries. Prior to the execution of a branch operation, the user program must  initialize  the  upper  bits  of  the  STATUS  register  to cause   a   branch   to   the   desired   page.   An   alternative method is to use the PAGE instruction, which automati- cally  causes  branch  to  the  desired  page,  based  on  the value specified in the operand field. 5.1.2  Subroutine Stack The subroutine stack consists of eight 12-bit save regis- ters. A physical transfer of register contents from the pro- gram  counter  to  the  stack  or  vice  versa,  and  within  the stack, occurs on all operations affecting the stack, prima- rily calls and returns. The stack is physically and logically separate  from  data  RAM.  The  program  cannot  read  or write the stack. 5.2 Data Memory The data memory is a RAM-based register set consisting of  262  general-purpose  registers  and  nine  special-pur- pose registers. All of these registers are eight bits wide. The data memory is organized into 16 banks, designated Bank  0  through  Bank  F,  each  containing  16  registers, plus an additional bank of 16 “global” registers. Because the  registers  are  organized  into  banks  or  “files,”  these memory-mapped registers are called “file registers.” 5.2.1  Addressing Modes/FSR Each SX instruction that accesses a data memory regis- ter  contains  a  5-bit  field  in  the  instruction  opcode  that specifies  the  register  to  be  accessed.  The  abbreviation “fr”  (file  register)   represents  the  5-bit  register  address designator. For example, the instruction description “mov fr,W”  means  that  a  5-bit  value  or  label  must  be  substi- tuted for “fr” in the instruction, such as “mov $0F,W” (to move the contents of the working register W into file reg- ister 0Fh). There  are  three  different  addressing  modes,  called  the indirect,  direct,  and  semi-direct  modes.  The  addressing mode used for register access depends on the 5-bit “fr” value used in the instruction: •    indirect mode: fr = 00h •    direct mode (fr bit 4 = 0): fr = 01h through 0Fh •    semi-direct mode (fr bit 4 = 1): fr = 10h through 1Fh Figure   5-1   illustrates   the   data   memory   addressing scheme. For  indirect  addressing  (fr=00),  the  File  Select  Register (FSR) specifies the register to be accessed. FSR is an 8- bit,   memory-mapped   register   (at   address   04h)   which serves  as  an  8-bit  pointer  into  data  memory  for  indirect addressing.  In  this  mode,  the  global  register  bank  and Bank  1  through  Bank  F  are  accessible.  Bank  0  is  not accessible. For  direct  addressing  (fr=01-0F),  the  value  of  “fr”  itself specifies the register to be accessed, and the FSR regis- ter is ignored. For this addressing mode, only the global register bank is accessible. To gain access to any other bank,    you    must    use    either    indirect    or    semi-direct addressing. For semi-direct addressing (fr=10-1F), the bank number is  selected  by  the  four  high-order  bits  of  FSR,  and  the register within that bank is selected by the four low-order bits   of   “fr.”   In   other   words,   the   register   address   is obtained  by  combining  the  four  high-order  bits  of  FSR with  the  four  low-order  bits  of  “fr”.  In  this  addressing mode,  the  low-order  bits  of  FSR  are  ignored.  Bank  0 through  Bank  F  are  accessible,  but  the  global  register bank is not accessible. Figure  5-1  shows  how  register  addressing  works  in  the indirect,  direct,  and  semi-direct  modes.  The  16  global registers  are  always  accessible  by  direct  addressing, regardless of what is contained in the FSR register. The global registers are also accessible with indirect address- ing, but they are not accessible with semi-direct address- ing. Of the 16 global registers, nine are special-purpose registers (RTCC, PC, STATUS, and so on), and  six are general-purpose  registers.  Location  00  is  used  for  indi- rect  addressing  (INDF).  All  of  the  registers  in  Bank  0 though Bank F are general-purpose registers. To change the contents of the FSR register, the program can either write an eight-bit value to the FSR register or use  the  “bank”  instruction.  The  “bank”  instruction  writes bits 4, 5, and 6 in the FSR register. Bit 7 of FSR is used to  select  the  upper  or  lower  “bank”  of  memory  banks. Thus, to change from one upper bank to another, only a single “bank” instruction is required. To change from one upper bank to a lower bank, the “bank” instruction must be followed by “setb FSR.7”.