© 2000 Scenix Semiconductor, Inc. All rights reserved. - 17 - www.scenix.com SX48BD/SX52BD/SX52BD75/SX52BD100 4.6 FUSEX WORD (READ/PROGRAM VIA PROGRAMMING COMMAND) 4.7 DEVICE ID Word (Hard-Wired Read-Only Via Programming Command)- Part ID Code 4.8 User Code ID Locations 1000h to 100Fh are allocated for user code ID. IRCTRIM2  SLEEPCLK  IRCTRIM1:IRCTRIM0   Unused CF BOR1:BOR0  BORTR1:BORTR0 DRT1:DRT0 11 10 9 8 7 6 5 4 3 2 1 0 IRCTRIM2: IRCTRIM0 Internal RC Oscillator Trim. This 3-bit field adjusts the operation of the internal RC oscillator to make it operate within the target frequency range of typically 4.0 MHz plus or minus 8%. Parts are shipped from the factory untrimmed. The device relies on the programming tool to provide trimming. 100b = 111b = 011b = maximum frequency typical minimum frequency SLEEPCLK Sleep Clock Disable. 0 = enable operation of the crystal/resonator clock during power down mode (to allow fast start- up). 1 = disable crystal/resonator clock operation during power down mode (to reduce power con- sumption). CF Carry Flag ADD/SUB enable 0 = carry bit input to ADD and SUB instructions. 1 = ADD and SUB without carry BOR1: BOR0 Sets the Brown Out Reset threshold voltage 00b = 4.1V 01b = 2.4V 10b = 2.2V 11b = BOR disabled BORTR1: BORTR0 Brown-Out trim bits (parts are shipped out of factory untrimmed). 01b = 00 = 11 = minimum threshold voltage 10b = maximum threshold voltage DRT1:DRT0 Delay Reset Timer (DRT) timeout period. Specifies the time from de-assertion of reset to start code execution. 10b = 0.25 msec 11b = 18 msec 00b = 60 msec 01b = 1 sec 0 0 0 0 0 0 0 0 0 0 1 0 11 10 9 8 7 6 5 4 3 2 1 0