© 2000 Scenix Semiconductor, Inc. All rights reserved. - 15 - www.scenix.com SX48BD/SX52BD/SX52BD75/SX52BD100 4.3 OPTION Register . Upon reset, all bits in the OPTION register are set to 1. 4.4 DEVICE CONFIGURATION AND ID REGISTERS The  SX  device  has  two  registers  (FUSE,  FUSEX)  that control  functions  such  as  clock  oscillator  configuration. These registers are not programmable “on the fly” during normal device operation. Instead, the FUSE and FUSEX registers  can  only  be  accessed  when  the  SX  device  is being  programmed.  The  DEVICE  ID  register  is  a  read- only, hard-wired register, defined during the manufactur- ing process. Locations 1000h to 100Fh are allocated for user code ID. RTW     RTE _IE RTS     RTE _ES PSA     PS2 PS1 PS0 Bit 7 Bit 0 Bit 7: RTW RTCC/W register selection: 0 = Register 01h addresses W 1 = Register 01h addresses RTCC Bit 6: RTE_IE RTCC interrupt enable: 0 = RTCC roll-over interrupt is en- abled 1 = RTCC roll-over interrupt is dis- abled Bit 5: RTS RTCC increment select: 0 = RTCC increments on internal in- struction cycle 1 = RTCC increments upon transition on RTCC pin Bit 4: RTE_ES RTCC edge select: 0 = RTCC increments on low-to-high transitions 1 = RTCC increments on high-to-low transitions Bit 3: PSA Prescaler Assignment: 0 = Prescaler is assigned to RTCC, with divide rate determined by PS0- PS2 bits 1 = Prescaler is assigned to WDT, and divide rate on RTCC is 1:1 Bits 2-0: PS2-PS0  Prescaler divider (see Table4-2) Table 4-2.  Prescaler Divider Ratios PS2, PS1, PS0 RTCC Divide Rate Watchdog Timer Divide Rate Approx. Watchdog Timeout (sec) 000 1:2 1:1 0.016 001 1:4 1:2 0.032 010 1:8 1:4 0.064 011 1:16 1:8 0.128 100 1:32 1:16 0.256 101 1:64 1:32 0.5 110 1:128 1:64 1.0 111 1:256 1:128 2.0