3 Data Memory
Addressing The FSR register is used to specify the
3-bit bank number for direct
addressing, or the full 8-bit address for
indirect addressing. For direct addressing, the three high-
order bits of FSR specify the bank
number, and the instruction opcode
(“fr” value) specifies the 5-bit address
of the register within the selected bank.
The five low-order bits of FSR are
ignored in this addressing mode. For indirect addressing, the FSR register specifies the full 8-bit address
of the register  being accessed. The data memory addressing can be
divided into three categories: indirect,
direct, and semi-direct. For direct addressing the 5-bit “fr”
value within the instruction specifies the address to be accessed and the FSR register is ignored. For this addressing
mode, only the global register bank is accessible. For indirect addressing, the FSR register specifies the register to be
accessed. In this mode, the global
register bank and Bank 1 through Bank F are accessible. Bank 0 is not
accessible. For semi-direct addressing, the bank number is selected by the four high- order bits of FSR, and the register
within that bank is selected the four
low-order bits of “fr”. Bank 0 through
Bank F is accessible, but the global
register bank is not accessible. BANK Instruction BANK instruction modifies bits 5, 6
and 7 of the FSR. BANK instruction modifies bits 4, 5
and 6 of the FSR. FSR bit 7 is user
selectable. RTCC Rollover
Interrupt Pending
Bit    No RTCC rollover interrupt pending
bit. Offers RTCC rollover interrupt
pending bit (RTCCOV bit in T1CNTB
register). 16-bit Multi-
Function Timers None. Contains Two. Bidirectional I/O
Ports Ports A, B, C. Ports A, B, C, D, E. Interrupt Sources RTCC, External (8 pins). RTCC, External (8 pins), Timer T1,
Timer T2. Interrupt Context
Shadow FSR, STATUS, W and PC shadowed. FSR, STATUS, W, MODE and PC
shadowed. Packages 18 SDIP/SOIC, 20 SSOP, 28
SDIP/SOIC, 28 SSOP 48 TQFP, 52 PQFP