© 2000 Scenix Semiconductor, Inc. All rights reserved. - 10 - www.scenix.com SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 PLP_A, PLP_B, and PLP_C: Pullup Enable Registers
(MODE=0Eh)
Each  register  bit  determines  whether  an  internal  pullup
resistor is connected to the pin. Set the bit to 1 to discon-
nect the pullup resistor or clear the bit to 0 to connect the
pullup resistor.
LVL_A, LVL_B, and LVL_C: Input Level Registers
(MODE=0Dh)
Each register bit determines the voltage levels sensed on
the  input  port,  either  TTL  or  CMOS,  when  the  Schmitt
trigger option is disabled. Program each bit according to
the type of device that is driving the port input pin. Set the
bit to 1 for TTL or clear the bit to 0 for CMOS.
ST_B and ST_C: Schmitt Trigger Enable Registers
(MODE=0Ch)
Each  register  bit  determines  whether  the  port  input  pin
operates with a Schmitt trigger. Set the bit to 1 to disable
Schmitt trigger operation and sense either TTL or CMOS
voltage levels; or clear the bit to 0 to enable Schmitt trig-
ger operation.
WKEN_B: Wakeup Enable Register (MODE=0Bh)
Each   register   bit   enables   or   disables   the   Multi-Input
Wakeup/Interrupt (MIWU) function for the corresponding
Port B input pin. Clear the bit to 0 to enable MIWU opera-
tion  or  set  the  bit  to  1  to  disable  MIWU  operation.  For
more information on using the Multi-Input Wakeup/Inter-
rupt function, see Section 7.0.
WKED_B: Wakeup Edge Register (MODE=0Ah)
Each register bit selects the edge sensitivity of the Port B
input pin for MIWU operation. Clear the bit to 0 to sense
rising (low-to-high) edges. Set the bit to 1 to sense falling
(high-to-low) edges. WKPND_B: Wakeup Pending Bit Register
(MODE=09h)
When  you  access  the  WKPND_B  register  using  MOV
!RB,W, the CPU does an exchange between the contents
of  W  and  WKPND_B.  This  feature  lets  you  read  the
WKPND_B register contents. Each bit indicates the sta-
tus  of  the  corresponding  MIWU  pin.  A  bit  set  to  1  indi-
cates    that    a    valid    edge    has     occurred    on    the
corresponding  MIWU  pin,  triggering  a  wakeup  or  inter-
rupt.  A  bit  set  to  0  indicates  that  no  valid  edge  has
occurred on the MIWU pin.
CMP_B: Comparator Register (MODE=08h)
When   you   access   the   CMP_B   register   using   MOV
!RB,W, the CPU does an exchange between the contents
of W and CMP_B. This feature lets you read the CMP_B
register  contents. Clear bit  7  to enable  operation  of the
comparator. Clear bit 6 to place the comparator result on
the RB0 pin. Bit 0 is a result bit that is set to 1 when the
voltage on RB2 is greater than RB1, or cleared to 0 oth-
erwise. (For more information using the comparator, see
Section 11.0.)
3.2.3  Port Configuration Upon Reset
Upon reset, all the port control registers are initialized to
FFh. Thus, each pin is configured to operate as a high-
impedance input that senses TTL voltage levels, with no
internal pullup resistor connected. The MODE register is
initialized to 0Fh, which allows immediate access to the
data direction registers using the “MOV !rx,W” instruction.